- F
- FCCM
- 1995
- IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95)
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IEEE Symposium on FPGA's for Custom Computing Machines (FCCM '95) Napa Valley, California April 19-April 21 ISBN: 0-8186-7086-X Table of Contents
 | Session 1: Custom Computing Platforms |
A. Lew, Dept. of Inf. & Comput. Sci., Hawaii Univ., Honolulu, HI, USA pp. 0002
T.H. Drayer, Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
J.G. Tront, Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
W.E. King, IV, Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
R.W. Conners, Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA pp. 0011
J.M. Carrera, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
E.J. Martinez, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
S.A. Fernandez, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
J.M.M. Chaus, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain pp. 0020
 | Session 2: Custom Computing Platforms |
R. Amerson, Hewlett-Packard Co., Palo Alto, CA, USA
P. Kuekes, Hewlett-Packard Co., Palo Alto, CA, USA
G. Snider, Hewlett-Packard Co., Palo Alto, CA, USA pp. 0032
B. Box, Lockheed Sanders Avionics, Nashua, NH, USA pp. 0039
 | Session 3: Signal Transport |
Chun-Chao Yeh, Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Chun-Hsing Wu, Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Jie-Yong Juang, Dept. of Comput. Sci. & Inf. Eng., Nat. Taiwan Univ., Taipei, Taiwan pp. 0056
J. Li, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
C.-K. Cheng, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA pp. 0061
K. Hayashi, NTT Opt. Network Syst. Labs., Yokosuka, Japan
T. Miyazaki, NTT Opt. Network Syst. Labs., Yokosuka, Japan
K. Yamada, NTT Opt. Network Syst. Labs., Yokosuka, Japan
N. Ohta, NTT Opt. Network Syst. Labs., Yokosuka, Japan pp. 0068
 | Session 4: Run-Time Reconfiguration |
J.D. Hadley, Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
B.L. Hutchings, Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA pp. 0078
B. Schoner, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
C. Jones, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
J. Villasenor, Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA pp. 0085
E. Lemoine, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
D. Merceron, Univ. des Sci. et Tech. du Languedoc, Montpellier, France pp. 0090
M.J. Wirthlin, Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA
B.L. Hutchings, Dept. of Electr. & Comput. Eng., Brigham Young Univ., Provo, UT, USA pp. 0099
 | Session 5: Applications I |
R.W. Wieler, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
Z. Zhang, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada
R.D. McLeod, Dept. of Electr. & Comput. Eng., Manitoba Univ., Winnipeg, Man., Canada pp. 0110
M. Dao, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
T.A. Cook, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
D. Silver, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
P.S. D'Urbano, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA pp. 0116
M. Shand, Res. Lab., Digital Equipment Corp., Paris, France pp. 0125
 | Session 6: Compiler Issues I |
D. Galloway, Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada pp. 0136
S. Singh, Dept. of Comput. Sci., Glasgow Univ., UK pp. 0145
N. Shirazi, Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
A. Walters, Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA
P. Athanas, Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA pp. 0155
 | Session 7: Compiler Issues II |
W. Luk, Dept. of Comput., Imperial Coll. of Sci., Technol. & Med., London, UK pp. 0164
C. Iseli, Lab. de Syst. Logiques, Ecole Polytech. Federale de Lausanne, Switzerland
E. Sanchez, Lab. de Syst. Logiques, Ecole Polytech. Federale de Lausanne, Switzerland pp. 0173
N. Sitkoff, Div. of Eng., Brown Univ., Providence, RI, USA
M. Wazlowski, Div. of Eng., Brown Univ., Providence, RI, USA
A. Smith, Div. of Eng., Brown Univ., Providence, RI, USA
H. Silverman, Div. of Eng., Brown Univ., Providence, RI, USA pp. 0180
 | Session 8: Applications II |
R.D. Meier, Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA pp. 0190
H.A. Chow, Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
H. Alnuweiri, Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada
S. Casselman, Dept. of Electr. Eng., British Columbia Univ., Vancouver, BC, Canada pp. 0197
N.K. Ratha, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, US
A.K. Jain, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, US
D.T. Rover, Dept. of Comput. Sci., Michigan State Univ., East Lansing, MI, US pp. 0204
H. Schmit, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
D. Thomas, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA pp. 0214 Usage of this product signifies your acceptance of the Terms of Use.
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