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2010 East-West Design & Test Symposium
An approach for PSL assertion coverage analysis with high-level decision diagrams
St. Petersburg, Russia
September 17-September 20
ISBN: 978-1-4244-9555-9
| ASCII Text | x | ||
| "An approach for PSL assertion coverage analysis with high-level decision diagrams," East-West Design & Test Symposium, pp. 13-16, 2010 East-West Design & Test Symposium, 2010. | |||
| BibTex | x | ||
| @article{ 10.1109/EWDTS.2010.5742048, author = {}, title = {An approach for PSL assertion coverage analysis with high-level decision diagrams}, journal ={East-West Design & Test Symposium}, volume = {0}, year = {2010}, isbn = {978-1-4244-9555-9}, pages = {13-16}, doi = {http://doi.ieeecomputersociety.org/10.1109/EWDTS.2010.5742048}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - East-West Design & Test Symposium TI - An approach for PSL assertion coverage analysis with high-level decision diagrams SN - 978-1-4244-9555-9 SP13 EP16 PY - 2010 KW - specification languages KW - decision diagrams KW - formal verification KW - Property Specification Language KW - PSL assertion coverage analysis KW - high-level decision diagrams KW - quality assessment KW - simulation-based verification stimuli KW - design error debug KW - design verification flow KW - assertion representation KW - Measurement KW - Analytical models KW - Computational modeling KW - IEEE standards KW - Boolean functions KW - Hardware design languages KW - Integrated circuit modeling VL - 0 JA - East-West Design & Test Symposium ER - | |||
The paper presents an approach for assertion coverage analysis targeted at quality assessment of simulation-based verification stimuli and design error debug. The approach considers high-level decision diagrams based design verification flow and relies on temporally extended high-level decision diagrams for PSL assertion representation. The discussed case study illustrates the advantages of the proposed idea.
Index Terms:
specification languages,decision diagrams,formal verification,Property Specification Language,PSL assertion coverage analysis,high-level decision diagrams,quality assessment,simulation-based verification stimuli,design error debug,design verification flow,assertion representation,Measurement,Analytical models,Computational modeling,IEEE standards,Boolean functions,Hardware design languages,Integrated circuit modeling
Citation:
"An approach for PSL assertion coverage analysis with high-level decision diagrams," ewdts, pp.13-16, 2010 East-West Design & Test Symposium, 2010
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