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Proceedings of The 26th EUROMICRO Conference (EUROMICRO'00) Volume I-Volume 1
Maastricht, The Netherlands
September 05-September 07
ISBN: 0-7695-0780-8
Table of Contents
K1 Keynote
K2 Keynote
K3 Keynote
A. Hasman, University of Maastricht
R. Bindels, University of Maastricht
P. de Clercq, University of Maastricht
pp. 1020
K4 Keynote
K5 Keynote
A1 Decomposition-based Logic Synthesis
B1 System Design
L. Lavagno, Universit? di Udine
B. Pino, Universidad de Granada
L.M. Reyneri, Politecnico di Torino
A. Serra, Politecnico di Torino
pp. 1076
C1 Design Validation using Formal Methods
Wolfgang Günther, Albert-Ludwigs-University
Nicole Drechsler, Albert-Ludwigs-University
Rolf Drechsler, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 1100
Harald Vranken, Philips Research Laboratories
Tomás Garciá Garciá, Eindhoven University of Technology
Sjouke Mauw, Eindhoven University of Technology
Loe Feijs, Eindhoven University of Technology
pp. 1122
D1 Technology-Driven Logic Synthesis
E1 New Approaches to Logic Synthesis
Tadeusz Luba, Warsaw University of Technology
Claudio Moraga, Dortmund University
Svetlana Yanushkevich, Technical University of Szczecin
Vlad Shmerko, Technical University of Szczecin
Joanna Kolodziejczyk, Technical University of Szczecin
pp. 1156
V. Ocheretnij, University of Potsdam
M. Goessel, University of Potsdam
Vl. Saposhnikov, Railway Transportation State University
V. Saposhnikov, Railway Transportation State University
pp. 1172
F1 DFT and Testing
Janusz Sosnowski, Warsaw University of Technology
Tomasz Bech, Warsaw University of Technology
pp. 1180
Rolf Drechsler, Albert-Ludwigs-University
Wolfgang Günther, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 1188
J.P.M. Voeten, Eindhoven University of Technology
H.P.E. Vranken, Eindhoven University of Technology
pp. 1193
G1 FPGA-Targetted and Non-Binary Logic Design
José Ignacio Hidalgo, Universidad Complutense de Madrid
Juan Lanchares, Universidad Complutense de Madrid
Roman Hermida, Universidad Complutense de Madrid
pp. 1204
H. Selvaraj, University of Nevada at Las Vegas
B. Li, University of Nevada at Las Vegas
pp. 1212
Parallel Multiplier Designs Utilizing a Non-Binary Logic Scheme (See paper in Late Papers section, page xv)
H1 High Level Design
Frédéric Mallet, Universit? de Nice Sophia Antipolis
Daniel Gaffé, Universit? de Nice Sophia Antipolis
Fernand Boéri, Universit? de Nice Sophia Antipolis
pp. 1230
A2 FPGA-based Processors
B2 Memory-Oriented Architectures
Witawas Srisa-an, Illinois Institute of Technology
Chia-Tien Dan Lo, Illinois Institute of Technology
J. Morris Chang, Illinois Institute of Technology
pp. 1274
C2 Instruction Level Paralellism
Rafael Moreno, Universidad Complutense de Madrid
Luis Piñuel, Universidad Complutense de Madrid
Silvia del Pino, Universidad Complutense de Madrid
Francisco Tirado, Universidad Complutense de Madrid
pp. 1292
Sorin Cotofana, Delft University of Technology
Ben Juurlink, Delft University of Technology
Stamatis Vassiliadis, Delft University of Technology
pp. 1307
D2 Algorithm-Oriented Architectures
P.N. Mallón, University of Santiago de Compostela
M. Bóo, University of Santiago de Compostela
J.D. Bruguera, University of Santiago de Compostela
pp. 1324
Austin Kim, Illinois Institute of Technology
Morris Chang, Illinois Institute of Technology
pp. 1332
E2 Configurable Architectures
Gerald G. Pechanek, Billions of Operations Per Second, Inc.
Stamatis Vassiliadis, Delft University of Technology
pp. 1348
César Ortega-Sánchez, University of York
Andy Tyrrell, University of York
Daniel Mange, Swiss Federal Institute of Technology
André Stauffer, Swiss Federal Institute of Technology
Gianluca Tempesti, Swiss Federal Institute of Technology
pp. 1356
Simon Leung, University of Queensland
Adam Postula, University of Queensland
Ahmed Hemani, Royal Institute of Technology
pp. 1362
F2 High-Speed Processing
Stefania Perri, University of Calabria
Pasquale Corsonello, University of Reggio Calabria
Giuseppe Cocorullo, University of Calabria and IRECE-National Council of Research
pp. 1394
Stamatis Vassiliadis, Delft University of Technology
Ben Juurlink, Delft University of Technology
Edwin Hakkennes, Delft University of Technology
pp. 1400
G2 IP and Design Reuse
Rupesh S. Shelar, Silicon Automation Systems
Sacheendra Nath, Silicon Automation Systems
Jagmohan S. Nanaware, Silicon Automation Systems
pp. 1410
Rolf Drechsler, Albert-Ludwigs-University
Nicole Drechsler, Albert-Ludwigs-University
Elke Mackensen, Albert-Ludwigs-University
Tobias Schubert, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 1425
H2 Hot Topic: System C
Dirk W. Hoffmann, University of T?bingen
Jürgen Ruf, University of T?bingen
Thomas Kropf, University of T?bingen
Wolfgang Rosenstiel, University of T?bingen
pp. 1435
A3 Multimedia Networking (Transmission)
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