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25th Euromicro Conference (EUROMICRO '99)-Volume 1
Milan, Italy
September 08-September 10
ISBN: 0-7695-0321-7
Table of Contents
Workshop on Digital System Design: Architectures, Methods and Tools
Keynote
System Architecture Exploration
Peeter Ellervee, ESD, KTH-Electrum, Electrum
Ahmed Hemani, ESD, KTH-Electrum, Electrum
Francky Catthoor, IMEC and Katholieke Universiteit Leuven
pp. 1014
Special Architectures Poster Session
Kimmo Kuusilinna, Tampere University of Technology
Pasi Liimatainen, Tampere University of Technology
Timo Hämäläinen, Tampere University of Technology
Jukka Saarinen, Tampere University of Technology
pp. 1042
Mathias Kortke, Dresden University of Technology
Dirk Fimmel, Dresden University of Technology
Renate Merker, Dresden University of Technology
pp. 1046
John Glossner, IBM Research and Delft University of Technology
Stamatis Vassiliadis, Delft University of Technology
pp. 1057
Jose A. Boluda, Universit?t de Valencia
Fernando Pardo, Universit?t de Valencia
Francisco Blasco, Universit?t de Valencia
Joan Pelechano, Universit?t de Valencia
pp. 1071
Jens Schönherr, Fraunhofer Institut f?r Integrierte Schaltungen (IIS), Erlangen, Au?enstelle EAS
Ingo Schreiber, Fraunhofer Institut f?r Integrierte Schaltungen (IIS), Erlangen, Au?enstelle EAS
Eva Fordran, Fraunhofer Institut f?r Integrierte Schaltungen (IIS), Erlangen, Au?enstelle EAS
Bernd Straube, Fraunhofer Institut f?r Integrierte Schaltungen (IIS), Erlangen, Au?enstelle EAS
pp. 1075
Logic Synthesis for FPGAs and CLPDs
Special Architectures
Rong Lin, State University of New York at Geneseo
Kevin E. Kerr, Hewlett-Packard Company
Andre S. Botha, Questa Corporation
pp. 1112
Gloria Martínez, Universitat Jaume I
Germán Fabregat, Universitat Jaume I
Vicente Hernández, Universitat Polit?cnica de Valencia
pp. 1120
José Luis Núñez, Loughborough University
Claudia Feregrino, Loughborough University
Simon Jones, Loughborough University
Stephen Bateman, GateField Corporation
pp. 1126
A. Schwarz, University of Hamburg
B. Mertsching, University of Hamburg
M. Brucke, University of Oldenburg
W. Nebel, University of Oldenburg
J. Tschorz, University of Oldenburg
B. Kollmeier, University of Oldenburg
pp. 1133
Kees-Jan Van der Kolk, Delft University of Technology
Ed F.A. Deprettere, Delft University of Technology
Jeong-A Lee, Chosun University
pp. 1140
Logic Synthesis for FPGAs
J.A. Espejo, University Carlos III of Madrid.
L. Entrena, University Carlos III of Madrid.
E. San Millán, University Carlos III of Madrid.
E. Olias, University Carlos III of Madrid.
pp. 1161
CPU and Memory Architectures I
Specification and Modeling
Asheesh Khare, University of California at Irvine
Nicolae Savoiu, University of California at Irvine
Ashok Halambi, University of California at Irvine
Peter Grun, University of California at Irvine
Nikil Dutt, University of California at Irvine
Alex Nicolau, University of California at Irvine
pp. 1196
M.A. Sacristan, Universidad Polit?cnica de Madrid
V. Rodellar, Universidad Polit?cnica de Madrid
A. Diaz, Universidad Polit?cnica de Madrid
V. Garcia, Universidad Polit?cnica de Madrid
P. Gomez, Universidad Polit?cnica de Madrid
pp. 1209
CPU and Memory Architectures Poster Session
Øyvind Strøm, Norwegian University of Science and Technology
Audun Klauseie, Norwegian University of Science and Technology
Einar J. Aas, Norwegian University of Science and Technology
pp. 1232
Testing and Verification
George Economakos, National Technical University of Athens
George Papakonstantinou, National Technical University of Athens
pp. 1268
Logic and High Level Synthesis Poster Session
Embedded System Optimization and Prototyping
Luc Bianco, I3S, Universit? de Nice Sophia Antipolis
Michel Auguin, I3S, Universit? de Nice Sophia Antipolis
Alain Pegatoquet, I3S, Universit? de Nice Sophia Antipolis and VLSI Technology
pp. 1318
Reconfigurable Architectures
Till Harbaum, Technical University of Braunschweig
Detlef Meier, Technical University of Braunschweig
Matthias Prinke, Technical University of Braunschweig
Martina Zitterbart, Technical University of Braunschweig
pp. 1335
Christof Teuscher, Swiss Federal Institute of Technology
Jacques-Olivier Haenni, Swiss Federal Institute of Technology
Hector Fabio Restrepo, Swiss Federal Institute of Technology
Eduardo Sanchez, Swiss Federal Institute of Technology
Francisco J. Gómez, Universidad Autonoma de Madrid
pp. 1343
Decision Diagrams, Decomposition and Optimization
Rolf Drechsler, Albert-Ludwigs-University
Dragan Jankovic, Albert-Ludwigs-University
Radomir S. Stankovic, Albert-Ludwigs-University
pp. 1352
Rafal Rzechowski, Warsaw University of Technology
Tadeusz Luba, Warsaw University of Technology
Lech Jozwiak, Eindhoven University of Technology
pp. 1368
Specification and Modeling Poster Session
F. Muller, IRESTE University of Nantes
J.P. Calvez, IRESTE University of Nantes
D. Heller, IRESTE University of Nantes
O. Pasquier, IRESTE University of Nantes
pp. 1382
Young Moo Lee, Korea Advanced Institute of Science and Technology
Kyu Ho Park, Korea Advanced Institute of Science and Technology
pp. 1388
Francesco Curatelli, D.I.B.E. - University of Genova
Leonardo Mangeruca, D.I.B.E. - University of Genova
Marco Chirico, D.I.B.E. - University of Genova
pp. 1390
M. Sporer, Chemnitz University of Technology
K. Agsteiner, Chemnitz University of Technology
D. Monjau, Chemnitz University of Technology
M. Schwaar, Chemnitz University of Technology
pp. 1398
CPU and Memory Architectures 2
Marina Alonso, Universidad Polit?cnica de Valencia
Vicente Santonja, Universidad Polit?cnica de Valencia
pp. 1416
Julio Sahuquillo, Universidad Polit?cnica de Valencia
Ana Pont, Universidad Polit?cnica de Valencia
pp. 1424
Ryotaro Kobayashi, Nagoya University
Yukihiro Ogawa, Nagoya University
Hideki Ando, Nagoya University
Toshio Shimada, Nagoya University
Mitsuaki Iwata, Mihara Machinery Works, Mitsubishi Heavy Industries, Ltd.
pp. 1432
Tanguy Gilmont, Universit? Catholique de Louvain
Jean-Didier Legat, Universit? Catholique de Louvain
Jean-Jacques Quisquater, Universit? Catholique de Louvain
pp. 1449
System Synthesis and Validation Poster Session
L.J. Van Bokhoven, Eindhoven University of Technology
J.P.M. Voeten, Eindhoven University of Technology
M.C.W. Geilen, Eindhoven University of Technology
pp. 1463
Francisco Moya, Universidad de Castilla-La Mancha
Juan C. López, Universidad de Castilla-La Mancha
José M. Moya, Universidad Polit?cnica de Madrid
pp. 1472
Matthias Bauer, Infineon Technologies
Wolfgang Ecker, Infineon Technologies
Renate Henftling, Infineon Technologies
Andreas Zinn, Infineon Technologies
pp. 1477
Janusz Sosnowski, Warsaw University of Technology
Piotr Gawkowski, Warsaw University of Technology
pp. 1481
Christian Kreiner, Technical University of Graz
Christian Steger, Technical University of Graz
Reinhold Weiss, Technical University of Graz
pp. 1492
P.H.A. Van der Putten, Eindhoven University of Technology
J.P.M. Voeten, Eindhoven University of Technology
M.C.W. Geilen, Eindhoven University of Technology
M.P.J. Stevens, Eindhoven University of Technology
pp. 1496
High Level Synthesis
O. Peñalba, Universidad Complutense de Madrid
J. M. Mendías, Universidad Complutense de Madrid
R. Hermida, Universidad Complutense de Madrid
pp. 1504
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