A hardware implementation of a computational adaptive radial basis function network is presented. Using a standard CMOS technology, the core circuits and the essential parts of the learning algorithm are implemented by means of functional integration. The wiring complexity of the network is reduced by an additional output pattern layer. This structure also benefits the applied dynamic on-line learning algorithm. The weight storage implemented using floating gates is handled by an intelligent programming strategy. The characteristics of the suggested architecture have been verified by both simulations and measurements of a couple of test circuits. Applications of this kind of neural hardware can primarily be found where conventional techniques cannot be used due to their size or power consumption, e.g., for intelligent sensor systems.