CSDL - Proceedings E

Workshop A Program Committee (PDF)

pp. 1xxii

Workshop A Reviewers (PDF)

pp. 1xxii

Keynote Speech

Keynote

Session A.1: Combinational Logic Design

Solving Synthesis Problems with Genetic Algorithms (Abstract)

Lech Jóźwiak, Eindhoven University of Technology

Niek Ederveen, Eindhoven University of Technology

Adam Postuła, University of Queensland

pp. 10001

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Efficient Logic Synthesis for FPGAs with Functional Decomposition Based on Information Relationship Measures (Abstract)

Mariusz Rawski, Warsaw University of Technology

Tadeusz Łuba, Warsaw University of Technology

Lech Jóźwiak, Eindhoven University of Technology

Artur Chojnacki, Eindhoven University of Technology

pp. 10008

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An Efficient Approach to Decomposition of Multi-Output Boolean Functions with Large Sets of Bound Variables (Abstract)

Michael Burns, Portland State University

Marek Perkowski, Portland State University

Lech Jóźwiak, Technical University of Eindhoven

pp. 10016

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A Reconfiguarable Printed Character Recognition System Using a Logic Synthesis Tool (Abstract)

Henry Selvaraj, Monash University

Muthukumar Venkatesan, Monash University

pp. 10024

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Session A.2: Poster Presentation

Design Correctness of Digital Systems (Abstract)

Corrie Huijs, University of Twente

pp. 10030

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Performing High-Level Synthesis via Program Transformations within a Theorem Prover (Abstract)

Christian Blumenröhr, University of Karlsruhe

Dirk Eisenbiegler, University of Karlsruhe

pp. 10034

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Specification of Exception Handling in Grammar-Based Hardware Synthesis (Abstract)

Johnny ?berg, Royal Institute of Technology

Anshul Kumar, Indian Institute of Technology

Ahmed Hemani, Royal Institute of Technology

pp. 10038

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Rule Base Driven Conversion of an Object Oriented Design Data Structure into Standard Hardware Description Languages (Abstract)

A. C. Verschueren, Eindhoven University of Technology

pp. 10042

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Verification of Embedded Real-Time Systems Using Hardware/Software Cosimulation (Abstract)

Mohammed El Shobaki, M?lardalen University

pp. 10046

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Efficient Combinational Loops Handling for Cycle Precise Simulation of System on a Chip (Abstract)

Denis Hommais, Universit? Pierre et Marie Curie

Fr?d?ric P?trot, Universit? Pierre et Marie Curie

pp. 10051

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Grammar Based Modelling and Synthesis of Device Drivers and Bus Interfaces (Abstract)

Mattias O?Nils, Royal Institute of Technology

Johnny ?berg, Royal Institute of Technology

Axel Jantsch, Royal Institute of Technology

pp. 10055

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Optimal System-Level Synthesis of Digital Systems for Real-Time Applications (Abstract)

Armin Bender, University of Passau

pp. 10059

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A Uni.ed Component Modeling Approach for Performance Estimation in Hardware/Software Codesign (Abstract)

Jesper Grode, Technical University of Denmark

Jan Madsen, Technical University of Denmark

pp. 10065

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A FPGA Implementation of a Video Rate Multi-Target Tracking System (Abstract)

Joan Aranda, UPC

Joan Climent, UPC

Antoni Grau, UPC

pp. 10070

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Session A.3: High-Level Synthesis

An Approach to High-Level Synthesis Using Constraint Logic Programming (Abstract)

Krzysztof Kuchcinski, Link?ping University

pp. 10074

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Operation Binding and Scheduling for Low Power Using Constraint Logic Programming (Abstract)

Flavius Gruian, Link?ping University

Krzysztof Kuchcinski, Link?ping University

pp. 10083

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Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment (Abstract)

George Economakos, National Technical University of Athens

George Papakonstantinou, National Technical University of Athens

pp. 10091

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K. Olcoz, Universidad Complutense de Madrid

J. F. Tirado, Universidad Complutense de Madrid

pp. 10099

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An Improved Register-Transfer Level Functional Partitioning Approach for Testability (Abstract)

Tianruo Yang, Linköping University

Zebo Peng, Linköping University

pp. 10107

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Session A.4: Custom Computing Machines

Automated Synthesis of Interleaved Memory Systems for Custom Computing Machines (Abstract)

Adam Postula, University of Queensland

Song Chen, University of Queensland

Lech Jozwiak, Eindhoven University of Technology

David Abramson, Monash University

pp. 10115

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Image Convolution on FPGAs: The Implementation of a Multi-FPGA FIFO Structure (Abstract)

Arrigo Benedetti, Universit? di Modena and California Institute of Technology

Andrea Prati, Universit? di Modena

Nello Scarabottolo, Universit? di Modena

pp. 10123

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Pipeline Architecture of Specialized Reconfigurable Processors in FPGA Structures for Real-Time Image Pre-Processing (Abstract)

Kazimierz Wiatr, AGH Technical University of Cracow

pp. 10131

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Arithmetic Image Coding/Decoding Architecture Based on a Cache Memory (Abstract)

Roberto R. Osorio, University of Santiago de Compostela

Montserrat Bóoand, University of Santiago de Compostela

Javier D. Bruguera, University of Santiago de Compostela

pp. 10139

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Session A.5: System Level Design

Hardware Architecture Modelling Using an Object-Oriented Method (Abstract)

Fr?d?ric Mallett, Universit? de Nice-Sophia Antipolis

Fernand Boeri, Universit? de Nice-Sophia Antipolis

Jean-Fran?ois Duboc, VLSI Technology Inc.

pp. 10147

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System Level Modelling for Hardware/Software Systems (Abstract)

J.P.M. Voeten, Eindhoven University of Technology

P.H.A. van der Putten, Eindhoven University of Technology

M.C.W. Geilen, Eindhoven University of Technology

M.P.J. Stevens, Eindhoven University of Technology

pp. 10154

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Hardware-Softw are Run-Time Systems and Robotics: A Case Study (Abstract)

Vincent John Mooney III, Georgia Institute of Technology

Diego Ruspini, Stanford University

Oussama Khatib, Stanford University

Giovanni De Micheli, Stanford University

pp. 10162

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Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems (Abstract)

Petru Eles, Link?ping University

Krzysztof Kuchcinski, Link?ping University

Zebo Peng, Link?ping University

Alexa Doboli, University of Cincinnati

Paul Pop, Link?ping University

pp. 10168

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Session A.6: Poster Presentations

Minimization of Algorithmic State Machines (Abstract)

Samary Baranov, Center for Technological Education

pp. 10176

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How Faults can be Simulated in Self-Testable VLSI Digital Circuits? (Abstract)

Dariusz Bojanowicz, Silesian University

pp. 10180

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Experimental Evaluation of Pseudorandom Test Effectiveness (Abstract)

J. Sosnowski, Warsaw University of Technology

pp. 10184

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Entropy-Based Design of Low Power FSMs (Abstract)

Lilia Kashirova, Tallinn Technical University

Olga Tveretina, Kharkov Politechnical University

pp. 10188

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RSR: A New Rectilinear Steiner Minimum Tree Approximation for FPGA Placement and Global Routing (Abstract)

Juan de Vicente, E.T.S.I.A.N.

Juan Lanchares, Universidad Complutense de Madrid

Rom? Hermida, Universidad Complutense de Madrid

pp. 10192

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Modified Approach to Automata State Encoding for LUT FPGA Implementation (Abstract)

I. Lemberski, Riga Aviation University

pp. 10196

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Design of Virtual Digital Controllers Based on Dynamically Reconfigurable FPGAs (Abstract)

Valery Sklyarov, Aveiro University

Nuno Lau, Aveiro University

Ricardo Sal Monteiro, Aveiro University

Andreia Melo, Aveiro University

Arnaldo Oliveira, Aveiro University

Konstantin Kondratjuk, Aveiro University

pp. 10200

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The Impact of Area Optimization for the Power Consumption of Controllers (Abstract)

H.-Ch. Dahmen, The German National Research Center for Information Technology

U. Gl?ser, The German National Research Center for Information Technology

pp. 10204

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Extending a Monoprocessor Real-Time System in a Multiprocessing Environment, DSP-Based (Abstract)

S. Aiello, Chimera Collaboration

A. Anzalone, Chimera Collaboration

M. Bartolucci, Chimera Collaboration

G. Cardella, Chimera Collaboration

S. Cavallaro, Chimera Collaboration

E. De Filippo, Chimera Collaboration

S. Femino, Chimera Collaboration

C. Garusi, Chimera Collaboration

M. Geraci, Chimera Collaboration

F. Giustolisi, Chimera Collaboration

P. Guazzoni, Chimera Collaboration

M. Iacono Manno, Chimera Collaboration

G. Lanzalone, Chimera Collaboration

G. Lanzano, Chimera Collaboration

S. Lo Nigro, Chimera Collaboration

G. Manfredi, Chimera Collaboration

A. Pagano, Chimera Collaboration

M. Papa, Chimera Collaboration

S. Pirrone, Chimera Collaboration

G. Politi, Chimera Collaboration

F. Porto, Chimera Collaboration

F. Rizzo, Chimera Collaboration

S. Sambataro, Chimera Collaboration

G. Savino, Chimera Collaboration

L. Sperduto, Chimera Collaboration

C. Sutera, Chimera Collaboration

L. Zetta, Chimera Collaboration

pp. 10208

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A Useful Micropipeline Architecture to Implement DSP Algorithms (Abstract)

Chiu-sing Choy, Chinese University of Hong Kong

Tin-chak Pang, Chinese University of Hong Kong

Juraj Povazanec, Chinese University of Hong Kong

Cheong-fat Chan, Chinese University of Hong Kong

pp. 10212

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Session A.7: Applications

Control System for a Low Energy Particle Detector (Abstract)

S. S?nchez, Universidad de Alcal?

D. Meziat, Universidad de Alcal?

M. Carbajo, Universidad de Alcal?

J. Medina, Universidad de Alcal?

E. Bronchalo, Universidad de Alcal?

J. Rodr?guez-Pacheco, Universidad de Alcal?

L. del Peral, Universidad de Alcal?

pp. 10216

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DELFT-JAVA Link Translation Buffer (Abstract)

John Glossner, Lucent / Bell Labs and Delft University of Technology

Stamatis Vassiliadis, Delft University of Technology

pp. 10221

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Session A.8: Real-Time Embedded Systems

Verification of Real Time Controllers Against Timing Diagram Specifications Using Constraint Logic Programming (Abstract)

Eduard Cerny, Universit? de Montr?al

Fen Jin, Universit? de Montr?al

pp. 10229

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Rate Assignment for Embedded Reactive Real-Time Systems (Abstract)

Youngsoo Shin, Seoul National University

Kiyoung Choi, Seoul National University

pp. 10237

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Hardware to Software Migration with Real-Time Thread Integration (Abstract)

Alexander G. Dean, Carnegie Mellon University

John Paul Shen, Carnegie Mellon University

pp. 10243

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Session A.9: Seqential Logic Synthesis

Design of Self-Synchronized Component FSMs for Self-Timed Systems (Abstract)

Loc Bao Nguen, Intel Supercomputer

Marek Perkowski, Portland State University

Lech Jozwiak, Technical University of Eindhoven

pp. 10253

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Multi-Criterial State Assignment for Low Power FSM Design (Abstract)

Manfred Koegst, Fraunhofer-Institut Integrierte Schaltungen

G? Franke, Hochschule f?r Technik und Wirtschaft Dresden

Steffen R?, Fraunhofer-Institut Integrierte Schaltungen

Klaus Feske, Fraunhofer-Institut Integrierte Schaltungen

pp. 10261

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A New Approach to And/Or/Exor Factorization for Regular Arrays (Abstract)

Ning Song, Portland State University

Marek Perkowski, Portland State University

pp. 10269

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Session A.10: Processor and Parallel Architectures

On the Design Complexity of the Issue Logic of Superscalar Machines (Abstract)

Sorin Cotofana, Delft University of Technology

Stamatis Vassiliadis, Delft University of Technology

pp. 10277

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Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue (Abstract)

Toshinori Sato, Toshiba Microelectronics Engineering Laboratory

pp. 10285

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The Latency Hiding Effectiveness of Decoupled Access/Execute Processors (Abstract)

Joan-Manuel Parcerisa, Universitat Polit?cnica de Catalunya

Antonio Gonz?lez, Universitat Polit?cnica de Catalunya

pp. 10293

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Revolver: A High-Performance MIMD Architecture for Collision Free Computing (Abstract)

Johnny ?berg, Royal Institute of Technology

Peeter Ellervee, Royal Institute of Technology

pp. 10301

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Session A.11: Poster Presentations

A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Process (Abstract)

J. A. Maestro, Universidad Complutense

D. Mozos, Universidad Complutense

J. Septi?, Universidad Complutense

pp. 10309

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Hierarchical Conditional Dependency Graphs for Conditional Resource Sharing (Abstract)

Apostolos A. Kountouris, Universitaire de Beaulieu

Christophe Wolinski, Universitaire de Beaulieu

pp. 10313

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Formal Extraction of Memorizing Elements for Sequential VHDL Synthesis (Abstract)

Ludovic Jacomme, Universit? Pierre et Marie Curie

Fr?d?ric P?trot, Universit? Pierre et Marie Curie

Rajesh K. Bawa, Universit? Pierre et Marie Curie

pp. 10317

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Data Speculative Multithreaded Architecture (Abstract)

Pedro Marcuello, Universitat Polit?cnica de Catalunya

Antonio Gonz?lez, Universitat Polit?cnica de Catalunya

pp. 10321

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The Impact of a Realistic Cache Structure on a Statically Scheduled Architecture (Abstract)

Daniel Tate, University of Hertfordshire

Gordon Steven, University of Hertfordshire

Paul Findlay, University of Hertfordshire

pp. 10325

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How to Half the Latency of IEEE Compliant Floating-Point Multiplication (Abstract)

Peter-Michael Seidel, University of Saarland

pp. 10329

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Impact of Reducing Miss Write Latencies in Multiprocessors with Two Level Cache (Abstract)

Julio Sahuquillo, Universidad Polit?cnica de Valencia

Ana Pont, Universidad Polit?cnica de Valencia

pp. 10333

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Efficient High-Speed CMOS Design by Layout Based Schematic Method (Abstract)

Fenghao Mu, Linköping University

Christer Svensson, Linköping University

pp. 10337

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A Miniature Serial-Data SIMD Architecture (Abstract)

Per Larsson-Edefors, Link?ping University

pp. 10341

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Cache Probabilistic Modeling for Basic Sparse Algebra Kernels Involving Matrices with a Non Uniform Distribution (Abstract)

Ramón Doallo, Universidade da Coruña

Basilio B. Fraguela, Universidade da Coruña

Emilio L. Zapata, Universidad de Málaga

pp. 10345

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Session A.12: High-Level Synthesis II

Estimation and Consideration of Interconnection Delays during High-Level Synthesis (Abstract)

Jonas Hallberg, Link?ping University

Zebo Peng, Link?ping University

pp. 10349

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Design of Control Dominated Hardware Based on Formal Methods (Abstract)

Werner Grass, Universität Passau

Stefan Lenk, Universität Passau

Christine Sontheim, Universität Passau

pp. 10357

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A Method for Mapping DSP Algorithms into Application Specific Structures (Abstract)

Anatoli Sergyienko, National Technical University of Ukraine

Juri Kanevski, Technical University of Koszalin

Oleg Maslennikov, Technical University of Koszalin

Roman Wyrzykowski, Technical University of Czestochowa

pp. 10365

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Workshop B. Dependable Computing Systems

Message from the Workshop B Chair (PDF)

pp. 1xxiii

Workshop B Program Committee (PDF)

pp. 1xxiv

Workshop B Reviewers (PDF)

pp. 1xxiv

Keynote Speech: Design Testing and Evaluation Techniques for Software Reliability Engineering (Abstract)

Michael R. Lyu, Chinese University of Hong Kong

pp. 1xxxix

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Session B.1: Masking Techniques

Simulation of a Component-Oriented Voter Library for Dependable Control Applications (Abstract)

G. Latif-Shabgahi, University of Sheffield

J.M. Bass, University of Sheffield

S. Bennett, University of Sheffield

pp. 10372

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The EFTOS Voting Farm: A Software Tool for Fault Masking in Message Passing Parallel Environments (Abstract)

Vincenzo De Florio, Katholieke Universiteit Leuven

Geert Deconinck, Katholieke Universiteit Leuven

Rudy Lauwereins, Katholieke Universiteit Leuven

pp. 10379

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Generating Multiple Diverse Software Versions with Genetic Programming (Abstract)

Robert Feldt, Chalmers University of Technology

pp. 10387

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Session B.2: Recovery Techniques

An Experimental Study about Diskless Checkpointing (Abstract)

Lu?s M. Silva, Universidade de Coimbra - POLO II

Jo?o Gabriel Silva, Universidade de Coimbra - POLO II

pp. 10395

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Distributed Checkpoint Algorithms to Avoid Roll-Back Propagation (Abstract)

Franco Zambonelli, Universitá di Modena

pp. 10403

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Dynamic Acceptance Tests for Complex Controllers (Abstract)

R. Stroph, University of York

T. Clarke, University of York

pp. 10411

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Session B.3: Fault Injection, Diagnosis and Debugging

Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System (Abstract)

D. Gil, Universidad Polit?cnica de Valencia

J. C. Baraza, Universidad Polit?cnica de Valencia

J. V. Busquets, Universidad Polit?cnica de Valencia

P. J. Gil, Universidad Polit?cnica de Valencia

pp. 10418

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On-the-Fly Model Checking of Program Runs for Automated Debugging (Abstract)

M. Frey, Technische Universität München

B.-H. Schlingloff, Universität Bremen

pp. 10426

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Session B.4: Development Approaches

On the Effectiveness of Slicing Hierarchical State Machines: A Case Study (Abstract)

Mats P.E. Heimdahl, University of Minnesota

Jeffrey M. Thompson, University of Minnesota

Michael W. Whalen, University of Minnesota

pp. 10435

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Engineering Safe, Real-Time Distributed Control Systems (Abstract)

Peter Croll, University of Sheffield

Chris Rudram, University of Sheffield

Colin Chambers, University of Sheffield

Naoshi Uchihira, University of Sheffield

pp. 10445

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Towards Standard-Based Specification and Design of Embedded Real-Time Systems (Abstract)

Roman Gumzej, University of Maribor

Matjaž Colnarič, University of Maribor

Domen Verber, University of Maribor

Wolfgang A. Halang, Fern Universität Hagen

pp. 10453

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Session B.5: Fault Treatment

A 32-Bit Risc Processor with Concurrent Error Detection (Abstract)

A. Maamar, University of Newcastle

G. Russell, University of Newcastle

pp. 10461

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An Experimental Investigation of Message Latencies in the Totem Protocol in the Presence of Faults (Abstract)

Holger Karl, Humboldt-Universität zu Berlin

Matthias Werner, Humboldt-Universität zu Berlin

Lars Küttner, Humboldt-Universität zu Berlin

pp. 10468

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Approaches for Scheduling of Triggered Transactions in Real-Time Active Database Systems (Abstract)

Kam-yiu Lam, City University of Hong Kong

Tony S.H. Lee, City University of Hong Kong

pp. 10476

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