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23rd EUROMICRO Conference '97 New Frontiers of Information Technology
A VLSI implementation of an arithmetic coder for image compression
Budapest, HUNGARY
September 01-September 04
ISBN: 0-8186-8129-2
ASCII Text
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M. Peon, R.R. Osorio, J.D. Bruguera, "A VLSI implementation of an arithmetic coder for image compression," EUROMICRO Conference, pp. 591, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997.
 
 
BibTex
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@article{ 10.1109/EURMIC.1997.617380,
author = {M. Peon and R.R. Osorio and J.D. Bruguera},
title = {A VLSI implementation of an arithmetic coder for image compression},
journal ={EUROMICRO Conference},
volume = {0},
year = {1997},
issn = {1089-6503},
pages = {591},
doi = {http://doi.ieeecomputersociety.org/10.1109/EURMIC.1997.617380},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - CONF
JO - EUROMICRO Conference
TI - A VLSI implementation of an arithmetic coder for image compression
SN - 1089-6503
SP
EP
A1 - M. Peon,
A1 - R.R. Osorio,
A1 - J.D. Bruguera,
PY - 1997
KW - arithmetic codes; VLSI implementation; arithmetic coder; image compression; multilevel alphabet; redundant arithmetic; cumulative probabilities; interval range; interval left point; updating; module delays; design speed; chip area; operating frequency; 39 MHz
VL - 0
JA - EUROMICRO Conference
ER -
 
M. Peon, Dept. of Electron. & Comput., Santiago de Compostela Univ., Spain
R.R. Osorio, Dept. of Electron. & Comput., Santiago de Compostela Univ., Spain
J.D. Bruguera, Dept. of Electron. & Comput., Santiago de Compostela Univ., Spain
Arithmetic coding is an efficient data compression technique. This paper describes the VLSI implementation of an arithmetic coder for a multilevel alphabet (256 symbols). The design we propose is based on the use of redundant arithmetic and the development of new schemes for storing and updating the cumulative probabilities and updating the range and left point of the interval. The use of redundant arithmetic reduces the delays of the modules, so the speed of the design is improved. The resulting chip has an area of 31 mm/sup 2/ and a operating frequency of 39 MHz.
Index Terms:
arithmetic codes; VLSI implementation; arithmetic coder; image compression; multilevel alphabet; redundant arithmetic; cumulative probabilities; interval range; interval left point; updating; module delays; design speed; chip area; operating frequency; 39 MHz
Citation:
M. Peon, R.R. Osorio, J.D. Bruguera, "A VLSI implementation of an arithmetic coder for image compression," euromicro, pp.591, 23rd EUROMICRO Conference '97 New Frontiers of Information Technology, 1997
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