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European Design Automation Conference with EURO-VHDL '95
Brighton, Great Britain
September 18-September 22
ISBN: 0-8186-7156-4
Table of Contents
Session D-01: System Level Synthesis
Chair: Ahmed Amine Jerraya, TIMA/INPG-UJF-CNRS, Grenoble, France
U. Weinmann, Comput. Sci. Res. Center, Karlsruhe Univ., Germany
O. Bringmann, Comput. Sci. Res. Center, Karlsruhe Univ., Germany
W. Rosenstiel, Comput. Sci. Res. Center, Karlsruhe Univ., Germany
pp. 2
M. Schwiegershausen, Lab. fur Informationstechnol., Hannover Univ., Germany
P. Pirsch, Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 8
P. Oehler, Frankfurt Univ., Germany
G. Grimm, Frankfurt Univ., Germany
K. Waldschmidt, Frankfurt Univ., Germany
pp. 14
Session D-02: Information Modeling
Chair: Franz Rammig, University GH, Paderborn, Germany
C.A. Giumale, Dept. of Comput. Sci., Bucharest Tech. Univ., Romania
H.J. Kahn, Dept. of Comput. Sci., Bucharest Tech. Univ., Romania
pp. 28
Z. Moosa, Dept. of Comput. Sci., Manchester Univ., UK
N. Filer, Dept. of Comput. Sci., Manchester Univ., UK
M. Brown, Dept. of Comput. Sci., Manchester Univ., UK
J. Heaton, Dept. of Comput. Sci., Manchester Univ., UK
J. Pye, Dept. of Comput. Sci., Manchester Univ., UK
pp. 34
Session D-03: Timing Issues in Synthesis
Chair: Kurt Antreich, Technical University of Munich, Germany
L. Rijnders, IMEC, Leuven, Belgium
Z. Sahraoui, IMEC, Leuven, Belgium
P. Six, IMEC, Leuven, Belgium
H. De Man, IMEC, Leuven, Belgium
pp. 48
V. Singhal, Cadence Berkeley Labs., Berkeley, CA, USA
C. Pixley, Cadence Berkeley Labs., Berkeley, CA, USA
A. Aziz, Cadence Berkeley Labs., Berkeley, CA, USA
R.K. Brayton, Cadence Berkeley Labs., Berkeley, CA, USA
pp. 54
N. Ramineni, Synopsys Inc., Beaverton, OR, USA
M. Chrzanowska-Jeske, Synopsys Inc., Beaverton, OR, USA
N. Buddi, Synopsys Inc., Beaverton, OR, USA
pp. 60
Session D-04: Placement and Routing
Chair: Hans van Nielen, Philips Semiconductors, Nijmegen, The Netherlands
T. Xue, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
E.S. Kuh, Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
pp. 74
M.J. Alexander, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.P. Cohoon, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
J.L. Ganley, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
G. Robins, Dept. of Comput. Sci., Virginia Univ., Charlottesville, VA, USA
pp. 80
N. Buddi, Dept. of Electr. Eng., Portland State Univ., OR, USA
M. Chrzanowska-Jeske, Dept. of Electr. Eng., Portland State Univ., OR, USA
C.L. Saxe, Dept. of Electr. Eng., Portland State Univ., OR, USA
pp. 86
Z. Moosa, Dept. of Comput. Sci., Manchester Univ., UK
D. Edwards, Dept. of Comput. Sci., Manchester Univ., UK
pp. 91
Session D-05: Different Aspects of Testability Improvements
Chair: Arno Kunzmann, FZI Karlsruhe, Germany
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 105
C. Gloster, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
F. Brglez, Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 111
F. Fummi, Dipartimento di Elettronica, Politecnico di Milano, Italy
U. Rovati, Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto, Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 117
Session D-06: Architectural Synthesis
Chair: Nikil Dutt, University of California at Irvine, USA
S. Bakshi, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 124
A.A. Duncan, Dept. of Eng., Aberdeen Univ., UK
D.C. Hendry, Dept. of Eng., Aberdeen Univ., UK
pp. 130
M. Vahidi, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
A. Orailoglu, Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
pp. 136
Session D-07: Partitioning and Floorplanning
Chair: Frank Johannes, Technical University of Munich, Germany
L.W. Hagen, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
J.-H. Huang, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
A.B. Kahng, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 144
U. Ober, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Darmstadt, Germany
M. Glesner, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Darmstadt, Germany
pp. 150
Session D-O8: Simulation and Partitioning of Hardware/Software Systems
Chair: Klaus Buchenrieder, Siemens AG, Munich, Germany
Th. Benner, Inst. fur Datenverarbeitungsanlagen, Braunschweig, Germany
R. Ernst, Inst. fur Datenverarbeitungsanlagen, Braunschweig, Germany
A. Osterling, Inst. fur Datenverarbeitungsanlagen, Braunschweig, Germany
pp. 164
J.-P. Soininen, VTT Electron., Oulu, Finland
T. Huttunen, VTT Electron., Oulu, Finland
K. Tiensyrja, VTT Electron., Oulu, Finland
H. Heusala, VTT Electron., Oulu, Finland
pp. 170
N.N. Binh, Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
M. Imai, Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
A. Shiomi, Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
N. Hikichi, Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan
pp. 176
Session D-09: Fault Modelling and Delay Testing
Chair: Irith Pomeranz, University of Iowa, USA
G. Spiegel, Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
A.P. Stroele, Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 184
A. Pierzynska, Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
S. Pilarski, Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 196
H. Wittmann, Dept. of Electr. Eng., Tech. Univ. Munchen, Germany
M. Henftling, Dept. of Electr. Eng., Tech. Univ. Munchen, Germany
pp. 202
Session D-11: Analog & Timing Modelling
Jacques Benkoski, EurEPIC, Gierès, France
J.M. Daga, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
M. Robert, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
D. Auvergne, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 216
Session D-12: ATPG and Speed-Up Techniques
Chair: Bernhard Eschermann, ABB Asea Brown Boveri, Baden-Dättwil, Switzerland
U. Glaser, German Nat. Res. Center for Comput. Sci., St. Augustin, Germany
H.T. Vierhaus, German Nat. Res. Center for Comput. Sci., St. Augustin, Germany
pp. 230
J. Sienicki, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
M. Bushnell, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
P. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
V. Agrawal, Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA
pp. 236
Z. Sahraoui, IMEC, Leuven, Belgium
P. Six, IMEC, Leuven, Belgium
I. Bolsens, IMEC, Leuven, Belgium
H. De Man, IMEC, Leuven, Belgium
pp. 242
M. Henftling, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
H. Wittmann, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
K.J. Antreich, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 248
Session D-13: Simulation and Debugging of System Descriptions
Chair: John Forrest, UMIST, University of Manchester, UK
G. Koch, Forschungszentrum Inf., Karlsruhe Univ., Germany
U. Kebschull, Forschungszentrum Inf., Karlsruhe Univ., Germany
W. Rosenstiel, Forschungszentrum Inf., Karlsruhe Univ., Germany
pp. 256
S. Schmerler, Forschungszentrum Inf., Karlsruhe Univ., Germany
Y. Tanurhan, Forschungszentrum Inf., Karlsruhe Univ., Germany
K.D. Muller-Glaser, Forschungszentrum Inf., Karlsruhe Univ., Germany
pp. 262
L. Schwoerer, Dortmund Univ., Germany
M. Luck, Dortmund Univ., Germany
H. Schroder, Dortmund Univ., Germany
pp. 268
Session D-14: Logic Synthesis and Optimization
Chair: Utz G. Baitinger, University of Stuttgart, Germany
T. Karoubalis, Comput. Technol. Inst., Patras Univ., Greece
G.Ph. Alexiou, Comput. Technol. Inst., Patras Univ., Greece
N. Kanopoulos, Comput. Technol. Inst., Patras Univ., Greece
pp. 282
G. Cabodi, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
S. Quer, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Camurati, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 288
E. Macii, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Poncino, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 294
J. Forrest, Dept. of Comput., Univ. of Manchester Inst. of Sci. & Technol., UK
pp. 600
Session D-15: Framework Architectures
Chair: Karl-Heinz Diener, FhG-IIS, Dresden, Germany
A. Bredenfeld, Gesellschaft fur Math. und Datenverarbeitung mbH, St. Augustin, Germany
pp. 308
J. Schubert, Comput. Sci. Res. Centre, Karlsruhe Univ., Germany
A. Kunzmann, Comput. Sci. Res. Centre, Karlsruhe Univ., Germany
W. Rosenstiel, Comput. Sci. Res. Centre, Karlsruhe Univ., Germany
pp. 314
Session D-16: Hardware/Software System Design
Chair: Ahmed Amine jerraya, TIMA/INPG, Grenoble, France
F. Vahid, Dept. of Comput. Sci., California Univ., Riverside, CA, USA
D.D. Gajski, Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 328
S. Srinivasan, Dept. of Electr. Eng., Princeton Univ., NJ, USA
N.K. Jha, Dept. of Electr. Eng., Princeton Univ., NJ, USA
pp. 334
Session D-17: EMC and Thermal Effects
Chair: Karl-Ludwig Paap, GMD, Sankt Augustin, Germany
E. Leroux, High Design Technol., Torino, Italy
F. Canavero, High Design Technol., Torino, Italy
G. Vecchi, High Design Technol., Torino, Italy
pp. 354
K.O. Petrosjanc, Moscow Univ. of Electron. & Math., Russia
I.A. Kharitonov, Moscow Univ. of Electron. & Math., Russia
N.I. Rybov, Moscow Univ. of Electron. & Math., Russia
P.P. Maltcev, Moscow Univ. of Electron. & Math., Russia
pp. 360
Session D-18: New Ideas in Synthesis
Chair: Pierre Paulin, SGS-Thomson Microelectronics, Grenoble, France
T. Gabler, Corp. Res. & Dev., Siemens AG, Munich, Germany
S. Marz-Rossel, Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 368
K. Shirai, Sch. of Sci. & Eng., Waseda Univ., Tokyo, Japan
J. Hiwatashi, Sch. of Sci. & Eng., Waseda Univ., Tokyo, Japan
pp. 380
Session V-01 : Simulation
Chairs: Jean Mermet, ECSI, Gieres, France and Victor Berman, Cadence Design Systems, Chelmsford, USA
S. Hodgson, Design Autom. Centre, ICL, Manchester, UK
Z. Shaar, Design Autom. Centre, ICL, Manchester, UK
A. Smith, Design Autom. Centre, ICL, Manchester, UK
pp. 394
J. Willis, Div. of Syst. Technol. & Archit., IBM Corp., Rochester, MN, USA
Zhiyuan Li, Div. of Syst. Technol. & Archit., IBM Corp., Rochester, MN, USA
Tsang-Puu Lin, Div. of Syst. Technol. & Archit., IBM Corp., Rochester, MN, USA
pp. 400
Session V-02: Formal Methods
Chair: Werner Damm, University of Oldenburg, Germany
Verification of the Futurebus + Cache Coherence Protocol
L. Arditi, CNRS, Nice Univ., Sophia Antipolis, France
H. Collavizza, CNRS, Nice Univ., Sophia Antipolis, France
pp. 414
P.T. Breuer, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
N.M. Madrid, ETSI Telecomunicacion, Univ. Politecnica de Madrid, Spain
pp. 420
Session V-03: Language Development
Chair: Jean-Michel Berge, France Telecom CNET, Meylan, France
G. Schumacher, Dept. of Comput. Sci., Carl von Ossietzky Univ., Oldenburg, Germany
W. Nebel, Dept. of Comput. Sci., Carl von Ossietzky Univ., Oldenburg, Germany
pp. 428
K. Agsteiner, Dept. of Comput. Sci., Tech. Univ. Chemnitz, Germany
D. Monjau, Dept. of Comput. Sci., Tech. Univ. Chemnitz, Germany
S. Schulze, Dept. of Comput. Sci., Tech. Univ. Chemnitz, Germany
pp. 436
Session V-04: Behavioral Synthesis from VHDL
Chair: Sabine Marz-Rossel, Siemens AG, Munich, Germany
P. Paulin, SGS-Thomson Microelectron., Crolles, France
J. Frehel, SGS-Thomson Microelectron., Crolles, France
M. Harrand, SGS-Thomson Microelectron., Crolles, France
E. Berrebi, SGS-Thomson Microelectron., Crolles, France
C. Liem, SGS-Thomson Microelectron., Crolles, France
F. Nacabul, SGS-Thomson Microelectron., Crolles, France
J.-C. Herluison, SGS-Thomson Microelectron., Crolles, France
pp. 444
P. Eles, Dept. of Comput. Sci. & Eng., Tech. Univ. of Timisoara, Romania
K. Kuchcinski, Dept. of Comput. Sci. & Eng., Tech. Univ. of Timisoara, Romania
Z. Peng, Dept. of Comput. Sci. & Eng., Tech. Univ. of Timisoara, Romania
A. Doboli, Dept. of Comput. Sci. & Eng., Tech. Univ. of Timisoara, Romania
pp. 452
W. Ecker, Corp. Res. & Dev., Siemens AG, Munich, Germany
M. Huber, Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 458
Session V-05: Design Techniques
Chairs: Serafin Olcoz, TGI, Madrid, Spain and Adam Pawlak, IMAG/ARTEMIS, Grenoble, France
V. Preis, Corp. Res. & Dev., Siemens AG, Munich, Germany
R. Henftling, Corp. Res. & Dev., Siemens AG, Munich, Germany
M. Schutz, Corp. Res. & Dev., Siemens AG, Munich, Germany
S. Marz-Rossel, Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 464
P. Kission, TIMA Lab., Grenoble, France
Hong Ding, TIMA Lab., Grenoble, France
A.A. Jerraya, TIMA Lab., Grenoble, France
pp. 470
M. Joshi, Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
H. Kobayashi, Dept. of Electr. & Comput. Eng., South Carolina Univ., Columbia, SC, USA
pp. 476
M. Mastretti, Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
M.L. Busi, Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
R. Sarvello, Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
M. Sturlesi, Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
S. Tomasello, Italtel Soc. Italiana Telecommun. SpA, Milan, Italy
pp. 482
Session V-07: System Level Design
Chair: Franz Rammig, University-GH-Paderborn, Germany
M.M.K. Hashmi, Design Autom. Centre, ICL, Manchester, UK
A.C. Bruce, Design Autom. Centre, ICL, Manchester, UK
pp. 490
F.R. Wagner, Inst. de Inf., Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 496
S. Olcoz, Dept. of Design Technol., TGI S.A., Madrid, Spain
L. Entrena, Dept. of Design Technol., TGI S.A., Madrid, Spain
L. Berrojo, Dept. of Design Technol., TGI S.A., Madrid, Spain
pp. 502
Session V-08: Modeling
Chair: Adam Pawlak, IMAG/ARTEMIS, Grenoble, France
V. Moser, Inst. of Microtechnology, Neuchatel Univ., Switzerland
H.P. Amann, Inst. of Microtechnology, Neuchatel Univ., Switzerland
P. Nussbaum, Inst. of Microtechnology, Neuchatel Univ., Switzerland
F. Pellandini, Inst. of Microtechnology, Neuchatel Univ., Switzerland
pp. 522
D. Galan, Dept. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectronica, Sevilla, Spain
C.J. Jimenez, Dept. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectronica, Sevilla, Spain
A. Barriga, Dept. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectronica, Sevilla, Spain
S. Sanchez-Solano, Dept. de Diseno de Circuitos Analogicos, Centro Nacional de Microelectronica, Sevilla, Spain
pp. 528
Session V-09: Verification and Validation
Chair: Eugenio Villar, University of Cantabria, Santander, Spain
R. Herrmann, Corp. Res. & Dev., Siemens AG, Munich, Germany
T. Reielts, Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 542
M. Schutz, Corp. Res. & Dev., Siemens AG, Munich, Germany
pp. 554
User Plenary Session
Chair: Gerry Musgrave, Brunel University and Abstract Hardware Ltd., UK
J. Van den Hurk, Philips Semicond., Product Concept & Application Lab. Eindhoven, Netherlands
E. Dilling, Philips Semicond., Product Concept & Application Lab. Eindhoven, Netherlands
pp. 568
J. Papanuskas, Automotive Equipment Div., Robert Bosch GmbH, Reutlingen, Germany
B. Mossner, Automotive Equipment Div., Robert Bosch GmbH, Reutlingen, Germany
T. Lindenkreuz, Automotive Equipment Div., Robert Bosch GmbH, Reutlingen, Germany
J. Hanisch, Automotive Equipment Div., Robert Bosch GmbH, Reutlingen, Germany
pp. 574
M. Romdhani, Avionics & Syst. Div., Aerospatiale, Toulouse, France
P. Chambert, Avionics & Syst. Div., Aerospatiale, Toulouse, France
A. Jeffroy, Avionics & Syst. Div., Aerospatiale, Toulouse, France
P. de Chazelles, Avionics & Syst. Div., Aerospatiale, Toulouse, France
A.A. Jerraya, Avionics & Syst. Div., Aerospatiale, Toulouse, France
pp. 585
P. Vanoostende, Adv. CAD for VLSI, Alcatel-Bell, Antwerpen, Belgium
G. Van Wauwe, Adv. CAD for VLSI, Alcatel-Bell, Antwerpen, Belgium
pp. 591
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