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  • EURO-DAC '96 European Design Automation Conference with EURO-VHDL '96
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EURO-DAC '96 European Design Automation Conference with EURO-VHDL '96
Geneva, Switzerland
September 16-September 20
ISBN: 0-8186-7573-X
Table of Contents
Session D-01 Analog and Mixed Mode Simulation
Vladimir B. Dmitriev-Zdorov, Theoretical Basis of Radioengineering Department of Taganrog State Radioengineering University
pp. 0015
Session D-02 Low Power Synthesis
Session D-03 Design Experience
Session D-04 Timing Modeling
Bernhard Wunder, Institut fuer Technik der Informationsverarbeitung
Gunther Lehmann, Institut fuer Technik der Informationsverarbeitung
Klaus D. Mueller-Glaser, Institut fuer Technik der Informationsverarbeitung
pp. 0072
Session D-05 Design Flow and Design Management
Session D-07 Partitioning
Session D-08 Logic & FSM Synthesis
Heinz-Josef Eikerling, {eikerlin,rosenstiel}@peanuts.informatik.uni-tuebingen.de
Wolfgang Rosenstiel, {eikerlin,rosenstiel}@peanuts.informatik.uni-tuebingen.de
pp. 0134
Andrew Crews, University of California, Santa Barbara, USA crews@corona.ece.ucsb.edu, forrest@ece.ucsb.edu
Forrest Brewer, University of California, Santa Barbara, USA crews@corona.ece.ucsb.edu, forrest@ece.ucsb.edu
pp. 0140
Session D-09 BDD Optimization Techniques
Session D-10 Codesign Methodology and Cospecification
Session D-11 System Level Design & Synthesis
Nand Kumar, Triquest Design Automation
Vinoo Srinivasan, Laboratory for Digital Design Environments, ECECS University of Cincinnati, Cincinnati, OH 45221-0030
Ranga Vemuri, Laboratory for Digital Design Environments, ECECS University of Cincinnati, Cincinnati, OH 45221-0030
pp. 0212
Session D-12 New Aspects on Testing
Angela Krstic, University of California, Santa Barbara, CA
Srimat T. Chakradhar, C&C Research Laboratories, NEC USA,
Kwang-Ting Cheng, University of California, Santa Barbara, CA
pp. 0220
Arno Kunzmann, Forschungszentrum Informatik (FZI) Email kunzmann@fzi.de
pp. 0227
Session D-13 Codesign Methodology & Cosimulation
D.Gareth Evans, Institute of Science and Technology - University of Manchester, UK
Peter N. Green, Institute of Science and Technology - University of Manchester, UK
Derrick Morris, Institute of Science and Technology - University of Manchester, UK
pp. 0264
Session D-15 Key Technologies and CAD of Microsystems
Session D-16 Asynchronous Synthesis and Storage Optimization
Tsung-Yi Wu, Tsing Hua University, Hsin-Chu, Taiwan 30043
Youn-Long Lin, Tsing Hua University, Hsin-Chu, Taiwan 30043
pp. 0296
Session D-17 Modelling, Simulation of Microsystems and Multi Layer Routing in PCBs
S. Meinzer, Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
A. Quinte, Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
M. Gorges-Schleuter, Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
W. Jakob, Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
W. Suess, Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
H. Eggert, Forschungszentrum Karlsruhe, Institut fuer Angewandte Informatik (IAI)
pp. 0322
Session D-18 Timing Issues in Synthesis
Hsiao-ping Juan, University of California, Irvine
Daniel D. Gajski, University of California, Irvine
Smita Bakshi, University of California, Irvine
pp. 0330
Session D-19 Physical Design for Deep Submicron
Session D-20 Architectural Synthesis Techniques
Smita Bakshi, University of California, Irvine
Daniel D. Gajski, University of California, Irvine
Hsiao-Ping Juan, University of California, Irvine
pp. 0370
Jui-Ming Chang, juiming@danube.usc.edu massoud@danube.usc.edu
Massoud Pedram, juiming@danube.usc.edu massoud@danube.usc.edu
pp. 0376
Anna Antola, Dipartimento di Elettronica e Informazione, Politecnico di Milano
Vincenzo Piuri, Dipartimento di Elettronica e Informazione, Politecnico di Milano
Mariagiovanna Sami, Dipartimento di Elettronica e Informazione, Politecnico di Milano
pp. 0382
Session D-22 CAD for Analog Circuit
Session V-01 Analysis Tools
Session V-02 Beyond VHDL
Session V-04 Fault Modeling and Design for Testability
E. de la Torre, Univ. Politecnica de Madrid, Spain
J. Calvo, Univ. Politecnica de Madrid, Spain
J. Uceda, Univ. Politecnica de Madrid, Spain
pp. 0456
T. Riesgo, Universidad PolitTcnica de Madrid
J. Uceda, Universidad PolitTcnica de Madrid
pp. 0462
Wendell C. Baker, {wbaker,newton}@eecs.berkeley.edu Department of Electrical Engineering and Computer Science University of California, Berkeley, 94720, USA
A. Richard Newton, {wbaker,newton}@eecs.berkeley.edu Department of Electrical Engineering and Computer Science University of California, Berkeley, 94720, USA
pp. 0470
Peter T. Breuer, Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
Carlos Delgado Kloos, Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
Natividad Martinez Madrid, Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
Andres Marin, Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
Luis Sanchez, Departamento de Ingenieria de Sistemas Telematicos ETSI Telecomunicacion, Universidad Politecnica de Madrid
pp. 0482
Session V-06 Modeling Methodologies
Maher Rahmouni, Coppe/UFRJ - Program of Electric Engineering
Polen Kission, Coppe/UFRJ - Program of Electric Engineering
Ahmed A. Jerraya, Coppe/UFRJ - Program of Electric Engineering
Luci Pirmez, Coppe/UFRJ - Program of Electric Engineering
A. Pedroza, Coppe/UFRJ - Program of Electric Engineering
A. Mesquita, Coppe/UFRJ - Program of Electric Engineering
pp. 0490
Konrad Feyerabend, Oldenburg University
Rainer Schloer, OFFIS, Escherweg 2, D-26121 Oldenburg, Rainer.Schloer@OFFIS.Uni-Oldenburg.DE
pp. 0496
Session V-07 Synthesis
Session V-08 System Level Design
Session V-09 VHDL & Mixed Signal Design
Author Index
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