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Fifth IEEE European Test Workshop (ETW'00)
Cascais, Portugal
May 23-May 26
ISBN: 0-7695-0701-8
Table of Contents
Session 1A Delay Testing and Test Scheduling
H. Speek, University of Twente
H. G. Kerkhoff, University of Twente
M. Sachdev, University of Waterloo
M. Shashaani, University of Waterloo
pp. 3
A. Virazel, Universit? Montpellier II
P. Girard, Universit? Montpellier II
C. Landrault, Universit? Montpellier II
S. Pravossoudovitch, Universit? Montpellier II
R. David, INPG - CNRS - UJF
pp. 9
Session 1B Scan and Functional Testing
Session 2A System Testing
A New Compression/Decompression Method for Non-Correlated Test Patterns: Application to Test Pins Expansion
M. Lajolo, NEC USA
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
L. Lavagno, Universit? di Udine
pp. 25
Session 3A IDDQ Testing
Antoni Ferré, Universitat Polit?cnica de Catalunya
Joan Figueras, Universitat Polit?cnica de Catalunya
pp. 33
Session 6A Analog and Mixed-Signal Testing
F. Azaïs, University of Montpellier
S. Bernard, University of Montpellier
Y. Bertrand, University of Montpellier
M. Renovell, University of Montpellier
pp. 53
Session 6B Core-Based Testing
Practical Methods and Tools for Embedded Macro Test
Session 7A Fault Simulation and FPGA Testing
Piet Engelke, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
Martin Keim, Infineon Technologies AG
pp. 63
M. Blyzniuk, State University ?Lvivska Politechnika?
M. Lobur, State University ?Lvivska Politechnika?
T. Cibaková, Institute of Informatics at Bratislava
E. Gramatová, Institute of Informatics at Bratislava
W. Kuzmicz, Warsaw University of Technology
W. Pleskacz, Warsaw University of Technology
J. Raik, Tallinn Technical University
R. Ubar, Tallinn Technical University
pp. 69
Session 7B Challenges in Deep Sub-Micron Testing
Anton Chichkov, Alcatel Microelectronics
Dirk Merlier, Alcatel Microelectronics
Peter Cox, Alcatel Microelectronics
pp. 91
Session 9A High Level Test
M. Boschini, ST Microelectronics
X. Yu, University of Illinois at Urbana-Champaign
E.M. Rudnick, University of Illinois at Urbana-Champaign
F. Fummi, Universit? di Verona
pp. 105
Yiorgos Makris, University of California at San Diego
Jamison Collins, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 111
Session 9B Memory Testing
Monica Lobetti Bodoni, Siemens Information and Communication Networks S.p.A.
Alfredo Benso, Politecnico di Torino
Silvia Chiusano, Politecnico di Torino
Stefano di Carlo, Politecnico di Torino
Giorgio di Natale, Politecnico di Torino
Paolo Prinetto, Politecnico di Torino
pp. 119
Session 10A BIST and Concurrent Testing
Ismet Bayraktaroglu, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 140
Session 10B Board Testing
Session 11 BIST Architecture
Tomasz Garbolino, Silesian University of Technology
Andrzej Hlawiczka, Silesian University of Technology
Adam Kristof, Silesian University of Technology
pp. 161
F. Corno, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
G. Squillero, Politecnico di Torino
M. Violante, Politecnico di Torino
pp. 167
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