CSDL - Proceedings E

Organizing Committee (PDF)

pp. x-xi

Steering Committee (PDF)

pp. xii

Program Committee (PDF)

pp. xii

ETS 2006 Paper Award (PDF)

pp. xiii

Test Technology Technical Council (PDF)

pp. xiv

Plenary Presentations

If It's All about Yield, Why Talk about Testing? (PDF)

Rene Segers, NXP Semiconductors

pp. 3

Electronics Design-for-Test: Past, Present and Future (PDF)

Ben Bennetts, ex-DFT Consultant, UK

pp. 4

Fault and Defect Diagnosis

Adaptive Debug and Diagnosis without Fault Dictionaries (Abstract)

Stefan Holst, Universitat Stuttgart, Germany

Hans-Joachim Wunderlich, Universitat Stuttgart, Germany

pp. 7-12

PDF

DERRIC: A Tool for Unified Logic Diagnosis (Abstract)

A. Rousset, Universite Montpellier II/CNRS, France

A. Bosio, Universite Montpellier II/CNRS, France

P. Girard, Universite Montpellier II/CNRS, France

C. Landrault, Universite Montpellier II/CNRS, France

S. Pravossoudovitch, Universite Montpellier II/CNRS, France

A. Virazel, Universite Montpellier II/CNRS, France

pp. 13-20

PDF

Mixed Signal DFT and Test

A Digitally Testable Capacitance-Insensitive Mixed-Signal Filter (Abstract)

Erik Schuler, Universidade Federal do Rio Grande do Sul, Brazil

Marcelo Negreiros, Universidade Federal do Rio Grande do Sul, Brazil

Pascal Nouet, Laboratoire d'Informatique, de Robotique et de Microelectronique de Montpellier, France

Luigi Carro, Universidade Federal do Rio Grande do Sul, Brazil

pp. 21-28

PDF

NoC Testing

Test Configurations for Diagnosing Faulty Links in NoC Switches (Abstract)

Jaan Raik, Tallinn University of Technology, Estonia

Raimund Ubar, Tallinn University of Technology, Estonia

Vineeth Govind, Tallinn University of Technology, Estonia

pp. 29-34

PDF

Optimization of NoC Wrapper Design under Bandwidth and Test Time Constraints (Abstract)

Fawnizu Azmadi Hussin, Nara Institute of Science and Technology, Japan

Tomokazu Yoneda, Nara Institute of Science and Technology, Japan

Hideo Fujiwara, Nara Institute of Science and Technology, Japan

pp. 35-42

PDF

Advances in RF Test

FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests (Abstract)

Ivo Koren, Infineon Technologies AG, Germany

Frank Demmerle, Infineon Technologies AG, Germany

Roland May, Infineon Technologies AG, Germany

Martin Kaibel, Infineon Technologies AG, Germany

Sebastian Sattler, Infineon Technologies AG, Germany

pp. 43-48

PDF

Digital Generation of Signals for Low Cost RF BIST (Abstract)

Marcelo Negreiros, Universidade Federal do Rio Grande do Sul, Brazil

Luigi Carro, Universidade Federal do Rio Grande do Sul, Brazil

Altamiro A. Susin, Universidade Federal do Rio Grande do Sul, Brazil

pp. 49-54

PDF

Variance Reduction for Supply Ramp Based Cheap RF Test Alternatives (Abstract)

Shaji Krishnan, NXP Semiconductors, The Netherlands

Rene Jonker, NXP Semiconductors, The Netherlands

Leon van de Logt, NXP Semiconductors, The Netherlands

pp. 55-62

PDF

Diagnosis and Debug

Parallel Scan-Like Testing and Fault Diagnosis Techniques for Digital Microfluidic Biochips (Abstract)

Tao Xu, Duke University, USA

Krishnendu Chakrabarty, Duke University, USA

pp. 63-68

PDF

Communication-Centric SoC Debug Using Transactions (Abstract)

Bart Vermeulen, NXP Semiconductors Research, The Netherlands

Kees Goossens, NXP Semiconductors Research, The Netherlands; Technical University Delft, The Netherlands

Remco van Steeden, Technical University of Twente, The Netherlands

Martijn Bennebroek, Philips Research, The Netherlands

pp. 69-76

PDF

Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories (Abstract)

Simulation and Verification

O. Ginez, Universite de Montpellier II/CNRS, France; ATMEL Rousset, France

J.-M. Daga, ATMEL Rousset, France

P. Girard, Universite de Montpellier II/CNRS, France

C. Landrault, Universite de Montpellier II/CNRS, France

S. Pravossoudovitch, Universite de Montpellier II/CNRS, France

A. Virazel, Universite de Montpellier II/CNRS, France

pp. 77-84

PDF

Memory Test

PPM Reduction on Embedded Memories in System on Chip (Abstract)

Said Hamdioui, Delft University of Technology, The Netherlands

Zaid Al-Ars, Delft University of Technology, The Netherlands

Javier Jimenez, Design of Systems on Silicon (DS2), Spain

Jose Calero, Design of Systems on Silicon (DS2), Spain

pp. 85-90

PDF

An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy (Abstract)

Philipp Ohler, University of Paderborn, Germany

Sybille Hellebrand, University of Paderborn, Germany

Hans-Joachim Wunderlich, University of Stuttgart, Germany

pp. 91-96

PDF

Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs (Abstract)

A. Ney, Universite de Montpellier II/CNRS, France

P. Girard, Universite de Montpellier II/CNRS, France

C. Landrault, Universite de Montpellier II/CNRS, France

S. Pravossoudovitch, Universite de Montpellier II/CNRS, France

A. Virazel, Universite de Montpellier II/CNRS, France

M. Bastian, Infineon Technologies, France

pp. 97-104

PDF

On-Line Testing and Self-Test

A Novel Approach for Online Sensor Testing Based on an Encoded Test Stimulus (Abstract)

N. Dumas, Lancaster University, UK

Z. Xu, Lancaster University, UK

K. Georgopoulos, Lancaster University, UK

R.J.T. Bunyan, QinetiQ, UK

A. Richardson, Lancaster University, UK

pp. 105-110

PDF

Selecting Power-Optimal SBST Routines for On-Line Processor Testing (Abstract)

A. Merentitis, University of Athens, Greece

N. Kranitis, University of Athens, Greece

A. Paschalis, University of Athens, Greece

D. Gizopoulos, University of Piraeus, Greece

pp. 111-116

PDF

Optimal Contexts for the Self-Test of Coarse Grain Dynamically Reconfigurable Processors (Abstract)

Tomoo Inoue, Hiroshima City University, Japan

Takashi Fujii, Hiroshima City University, Japan

Hideyuki Ichihara, Hiroshima City University, Japan

pp. 117-124

PDF

Fault Grading and Test Quality

A Seed-Selection Method to Increase Defect Coverage for LFSR-Reseeding-Based Test Compression (Abstract)

Zhanglei Wang, Duke University, USA

Krishnendu Chakrabarty, Duke University, USA

Michael Bienek, Advanced Micro Devices, USA

pp. 125-130

PDF

Ultra Fast Parallel Fault Analysis on Structurally Synthesized BDDs (Abstract)

Raimund Ubar, Tallinn University of Technology, Estonia

Sergei Devadze, Tallinn University of Technology, Estonia

Jaan Raik, Tallinn University of Technology, Estonia

Artur Jutman, Tallinn University of Technology, Estonia

pp. 131-136

PDF

Computation and Application of Absolute Dominators in Industrial Designs (Abstract)

Rene Krenz-Baath, NXP Semiconductors, Germany

Andreas Glowatz, NXP Semiconductors, Germany

Juergen Schloeffel, NXP Semiconductors, Germany

pp. 137-144

PDF

Diagnosis and Yield Improvement

Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement (Abstract)

Huaxing Tang, Mentor Graphics Corporation, USA

Sharma Manish, Mentor Graphics Corporation, USA

Janusz Rajski, Mentor Graphics Corporation, USA

Martin Keim, Mentor Graphics Corporation, USA

Brady Benware, Mentor Graphics Corporation, USA

pp. 145-150

PDF

Diagnostic Test Generation Based on Subsets of Faults (Abstract)

Irith Pomeranz, Purdue University, USA

Sudhakar M. Reddy, University of Iowa, USA

pp. 151-158

PDF

Single Event Upsets

Static and Dynamic Analysis of SEU Effects in SRAM-Based FPGAs (Abstract)

L. Sterpone, Politecnico di Torino, Italy

M. Violante, Politecnico di Torino, Italy

pp. 159-164

PDF

System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies (Abstract)

C.A. Lisboa, Universidade Federal do Rio Grande do Sul, Brazil

M.I. Erigson, Universidade Federal do Rio Grande do Sul, Brazil

L. Carro, Universidade Federal do Rio Grande do Sul, Brazil

pp. 165-172

PDF

Delay and Performance Test

Automatic Generation of Instructions to Robustly Test Delay Defects in Processors (Abstract)

Sankar Gurumurthy, The University of Texas at Austin, USA

Ramtilak Vemu, The University of Texas at Austin, USA

Jacob A. Abraham, The University of Texas at Austin, USA

Daniel G. Saab, Case Western Reserve University

pp. 173-178

PDF

On the Automatic Generation of Test Programs for Path-Delay Faults in Microprocessor Cores (Abstract)

P. Bernardi, Politecnico di Torino, Italy

M. Grosso, Politecnico di Torino, Italy

E. Sanchez, Politecnico di Torino, Italy

M. Sonza Reorda, Politecnico di Torino, Italy

pp. 179-184

PDF

Purely Digital BIST for Any PLL or DLL (Abstract)

Stephen Sunter, LogicVision, Inc.

Aubin Roy, LogicVision, Inc.

pp. 185-192

PDF

Embedded Tutorials

System-in-Package, a Combination of Challenges and Solutions (Abstract)

P. Cauvet, NXP Semiconductors, France

S. Bernard, LIRMM, University of Montpellier/CNRS, France

M. Renovell, LIRMM, University of Montpellier/CNRS, France

pp. 193-199

PDF

Embedded Tutorial: IC Test Cost Benchmarking (PDF)

Klaus Luther, Infineon Technologies AG, Germany

pp. 200

Wafer Level Reliability Screens (PDF)

Peter Maxwell, Micron Technology

pp. 201

Embedded Tutorial on Low Power Test (Abstract)

Nicola Nicolici, McMaster University, Canada

Xiaoqing Wen, Kyushu Institute of Technology, Japan

pp. 202-210

PDF

"Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC (Abstract)

ETS06 Best Paper

V. Kerzerho, LIRMM, University of Montpellier/CNRS, France; Philips France Semiconducteurs

P. Cauvet, Philips France Semiconducteurs

S. Bernard, LIRMM, University of Montpellier/CNRS, France

F. Azais, LIRMM, University of Montpellier/CNRS, France

M. Comte, LIRMM, University of Montpellier/CNRS, France

M. Renovell, LIRMM, University of Montpellier/CNRS, France

pp. 211-216

PDF

Author Index

Author Index (PDF)

pp. 217