This Article 
 Bibliographic References 
 Add to: 
Eleventh IEEE European Test Symposium (ETS'06)
A DFT Architecture for Asynchronous Networks-on-Chip
Southampton, United Kingdom
May 21-May 21
ISBN: 0-7695-2566-0
Xuan-Tu Tran, LETI - CEA, France
Jean Durupt, LETI - CEA, France
Francois BERTRAND Bertrand, LETI - CEA, France
Vincent Beroulle, LCIS -INPG, France
Chantal Robach, LCIS - INPG, France
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these network architectures.

To test the SoCs, the main challenge is to reach into the embedded cores (i.e, the IPs). In this case, the DFT techniques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT architecture is developed in order to ease the test of NoC architectures. The target of this test architecture is asynchronous NoC architectures that are implemented in GALS systems. The proposed architecture is therefore named ANoC-TEST and is implemented in QDI asynchronous circuits. In addition, this architecture can be used to test the computing resources of the networked SoCs. Some initial results and conclusions are also given.

Xuan-Tu Tran, Jean Durupt, Francois BERTRAND Bertrand, Vincent Beroulle, Chantal Robach, "A DFT Architecture for Asynchronous Networks-on-Chip," ets, pp.219-224, Eleventh IEEE European Test Symposium (ETS'06), 2006
Usage of this product signifies your acceptance of the Terms of Use.