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Eleventh IEEE European Test Symposium (ETS'06)
Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits
Southampton, United Kingdom
May 21-May 21
ISBN: 0-7695-2566-0
ASCII Text
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Erik Sch?, Daniel Scain Farenzena, Luigi Carro, "Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits," 2009 14th IEEE European Test Symposium, pp. 137-144, Eleventh IEEE European Test Symposium (ETS'06), 2006.
 
 
BibTex
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@article{ 10.1109/ETS.2006.19,
author = {Erik Sch? and Daniel Scain Farenzena and Luigi Carro},
title = {Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits},
journal ={2009 14th IEEE European Test Symposium},
volume = {0},
year = {2006},
issn = {1530-1877},
pages = {137-144},
doi = {http://doi.ieeecomputersociety.org/10.1109/ETS.2006.19},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
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TY - CONF
JO - 2009 14th IEEE European Test Symposium
TI - Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits
SN - 1530-1877
SP137
EP144
A1 - Erik Sch?,
A1 - Daniel Scain Farenzena,
A1 - Luigi Carro,
PY - 2006
KW - null
VL - 0
JA - 2009 14th IEEE European Test Symposium
ER -
 
Erik Sch?, Universidade Federal do Rio Grande do Sul, Brazil
Daniel Scain Farenzena, Universidade Federal do Rio Grande do Sul, Brazil
Luigi Carro, Universidade Federal do Rio Grande do Sul, Brazil
As microelectronics evolves smaller into the nanometric scale, external interferences starts to be harmful to the system expected behavior. As classical systems do not handle adequately faults caused by such sources, new topologies are proposed. Our present work proposes a solution for this problem consisting on the use of sigma-delta modulation in order to obtain a faulttolerance even in presence of multiple faults. This paper provides the mathematical analysis and demonstration to support the proposed approach.
Citation:
Erik Sch?, Daniel Scain Farenzena, Luigi Carro, "Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits," ets, pp.137-144, Eleventh IEEE European Test Symposium (ETS'06), 2006
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