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10th IEEE European Test Symposium (ETS'05)
Tallinn, Estonia
May 22-May 25
ISBN: 0-7695-2341-2
Table of Contents
SoC Testing
Raimund Ubar, Tallinn University of Technology
Tatjana Shchenova, Tallinn University of Technology
Gert Jervan, Link?ping University
Zebo Peng, Link?ping University
pp. 2-7
Urban Ingelsson, Linköpings Universitet
Sandeep Kumar Goel, Philips Research Labs
Erik Larsson, Linköpings Universitet
Erik Jan Marinissen, Philips Research Labs
pp. 8-13
Dan Zhao, University of Louisiana at Lafayette
Shambhu Upadhyaya, State University of New York at Buffalo
Martin Margala, University of Rochester
pp. 14-19
Advances in Fault and Defect Models
Gang Chen, University of Iowa
Sudhakar Reddy, University of Iowa
Irith Pomeranz, Purdue University
Janusz Rajski, Mentor Graphics Corporation
Piet Engelke, Albert-Ludwigs-University
Bernd Becker, Albert-Ludwigs-University
pp. 22-27
Daniel Arum?, Universitat Polit?cnica de Catalunya
Rosa Rodr?guez-Monta?, Universitat Polit?cnica de Catalunya
Joan Figueras, Universitat Polit?cnica de Catalunya
pp. 28-33
Victor H. Champac, National Institute for Astrophysics, Optics and Electronics
Antonio Zenteno, National Institute for Astrophysics, Optics and Electronics
José L. García, National Institute for Astrophysics, Optics and Electronics
pp. 34-40
Advanced Test Generation Issues
Low Cost Testing for Advanced Analog Circuits
G. Srinivasan, Georgia Institute of Technology
S. Cherubal, Texas Instruments
P. Variyam, Texas Instruments
M. Teklu, Texas Instruments
C. P. Wang, Texas Instruments
D. Guidry, Texas Instruments
A. Chatterjee, Georgia Institute of Technology
pp. 68-73
On-Line and BIST Techniques for MEMS
F. Mailly, Université Montpellier II
F. Aza?, Université Montpellier II
N. Dumas, Université Montpellier II
L. Latorre, Université Montpellier II
P. Nouet, Université Montpellier II
pp. 76-81
Defect and Dynamic Fault Testing
Jaan Raik, Tallinn University of Technology
Raimund Ubar, Tallinn University of Technology
Joachim Sudbrock, Tallinn University of Technology
Wieslaw Kuzmicz, Warsaw University of Technology
Witold Pleskacz, Warsaw University of Technology
pp. 96-101
Smita Krishnaswamy, University of Michigan
Igor L. Markov, University of Michigan
John P. Hayes, University of Michigan
pp. 102-107
SRAM Memory Testing
Luigi Dilillo, Universté de Montpellier II
Patrick Girard, Universté de Montpellier II
Serge Pravossoudovitch, Universté de Montpellier II
Arnaud Virazel, Universté de Montpellier II
pp. 116-121
A. Benso, Politecnico di Torino
A. Bosio, Politecnico di Torino
S. Di Carlo, Politecnico di Torino
G. Di Natale, Politecnico di Torino
P. Prinetto, Politecnico di Torino
pp. 122-127
Testing Regular Structures
Validation and Molecular Electronics
Fei Xin, University of Massachusetts at Amherst
Maciej Ciesielski, University of Massachusetts at Amherst
Ian G. Harris, University of California at Irvine
pp. 156-161
Fault Diagnosis
Grzegorz Mrugalski, Mentor Graphics Corporation
Artur Pogiel, Poznań University of Technology
Janusz Rajski, Mentor Graphics Corporation
Jerzy Tyszer, Poznań University of Technology
Chen Wang, Mentor Graphics Corporation
pp. 176-181
Xinyue Fan, Oxford University
Will Moore, Oxford University
Camelia Hora, Philips Research Labs
Guido Gronthoud, Philips Research Labs
pp. 182-187
SoC Testing and Secure ICs
David H?ly, ST Microelectronics and Universit? Montpellier II
Fr?d?ric Bancel, ST Microelectronics
Marie-Lise Flottes, Universit? Montpellier II
Bruno Rouzeyre, Universit? Montpellier II
pp. 190-195
Embedded Tutorials
Chuck Hawkins, University of New Mexico
Jaume Segura, University of the Balearic Islands
pp. 210-215
Author Index
Author Index (PDF)
pp. 229-230
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