CSDL - Proceedings E

Conference Organizers (PDF)

pp. ix

Program Committee (PDF)

pp. x

Group Posters (PDF)

pp. xi

Invited Talks

We Need Assurance (PDF)

Brian Snow, National Security Agency

pp. 3

The Failure of a Small Satellite and the Loss of a Space Science Mission (PDF)

Rich Katz, NASA

pp. 4

Evolvable Hardware for Industrial Applications

Dependable Reconfigurable Computing Design Diversity and Self Repair (PDF)

Subhasish Mitra, Intel Corporation and Stanford University

Edward J. McCluskey, Stanford University

pp. 5

Life, the Universe, and Everything: 4.5 Billion Years of Evolvable Hardware (PDF)

John D. Rummel, NASA Headquarters

pp. 6

Physical Support for Evolution in Reconfigurable Devices (PDF)

Peter Athanas, Virginia Polytechnic Institute and State University

pp. 7

Getting Most Out of Evolutionary Approaches (Abstract)

Xin Yao, University of Birmingham

Yong Liu, University of Aizu

pp. 8

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1. Evolution of Digital Systems

Evolvable Hardware for the Generation of Sequential Filter Circuits (Abstract)

Robert Thomson, University of Edinburgh

Tughrul Arslan, University of Edinburgh

pp. 17

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The Robustness of Small Developped SBlock Circuits Using Different Clocking Schemes (Abstract)

Piet van Remortel, Vrije Universiteit Brussel

Tom Lenaerts, Vrije Universiteit Brussel

Bernard Manderick, Vrije Universiteit Brussel

pp. 26

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Evolving Robust Digital Designs (Abstract)

Morten Hartmann, Norwegian University of Science and Technology

Pauline Haddow, Norwegian University of Science and Technology

Frode Eskelund, Norwegian University of Science and Technology

pp. 36

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Self-Assembling Circuits with Autonomous Fault Handling (Abstract)

Nicholas J. Macias, Cell Matrix Corporation

Lisa J. K. Durbeck, Cell Matrix Corporation

pp. 46

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On Two New Trends in Evolvable Hardware: Employment of HDL-Based Structuring, and Design of Multi-Functional Circuits (Abstract)

Adrian Stoica, California Institute of Technology

Didier Keymeulen, California Institute of Technology

Ricardo S. Zebulum, California Institute of Technology

M. I. Ferguson, California Institute of Technology

pp. 56

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Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic (Abstract)

Channakeshav, Rensselaer Polytechnic Institute

K. Zhou, Rensselaer Polytechnic Institute

R. Kraft, Rensselaer Polytechnic Institute

J. F. McDonald, Rensselaer Polytechnic Institute

pp. 60

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Evolutionary Technique to Elementary Coding of the Internal States of the State Machine (PDF)

Igor V. Vasiltsov, Ternopil Academy of National Economy

pp. 63

2. Evolution of Analog Systems

Evolving Circuits in Seconds: Experiments with a Stand-Alone Board-Level Evolvable System (Abstract)

Adrian Stoica, California Institute of Technology

Ricardo S. Zebulum, California Institute of Technology

M. I. Ferguson, California Institute of Technology

Didier Keymeulen, California Institute of Technology

Vu Duong, California Institute of Technology

pp. 67

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Intrinsic Evolution of Quasi DC Solutions for Transistor Level Analog Electronic Circuits Using a CMOS FPTA Chip (Abstract)

Jörg Langeheine, Heidelberg University

Karlheinz Meier, Heidelberg University

Johannes Schemmel, Heidelberg University

pp. 75

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Automated Design of Analog Circuits Using Cell-Based Structure (Abstract)

Hajime Shibata, Analog Devices K.K.

Soji Mori, Tokyo Institute of Technology

Nobuo Fujii, Tokyo Institute of Technology

pp. 85

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Application of the Univariate Marginal Distribution Algorithm to Analog Circuit Design (Abstract)

Lyudmilla Zinchenko, Taganrog State University of Radioengineering

Heinz Mühlenbein, Theoretical Foundation GMD Lab

Victor Kureichik, Taganrog State University of Radioengineering

Thilo Mahnig, Theoretical Foundation GMD Lab

pp. 93

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Chromosome Representation through Adjacency Matrix in Evolutionary Circuits Synthesis (Abstract)

A. Mesquita, Federal University of Rio de Janeiro

Fabio A. Salazar, Federal University of Rio de Janeiro

P. Paulo Canazio, Federal University of Rio de Janeiro

pp. 102

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Automatic Synthesis Using Genetic Programming of an Improved General-Purpose Controller for Industrially Representative Plants (Abstract)

3. Evolution of Controllers

Martin A. Keane, Econometrics Inc.

John R. Koza, Stanford University

Matthew J. Streeter, Genetic Programming Inc.

pp. 113

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Towards Evolvable Analog Fuzzy Logic Controllers (Abstract)

José Franco Machado do Amaral, Rio de Janeiro State University

Jorge Luís Machado do Amaral, Rio de Janeiro State University

Cristina C. Santini, Catholic University of Rio de Janeiro

Ricardo Tanscheit, Catholic University of Rio de Janeiro

Marley Maria R. Vellasco, Catholic University of Rio de Janeiro

Marco Aurélio C. Pacheco, Catholic University of Rio de Janeiro

pp. 123

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How to Evolve Safe Control Strategies (PDF)

G. W. Greenwood, Portland State University

X. Song, Portland State University

pp. 129

4. Real World Applications

An EHW Architecture for Real-Time GPS Attitude Determination Based on Parallel Genetic Algorithm (Abstract)

Jiangning Xu, University of Edinburgh

T. Arslan, University of Edinburgh

pp. 133

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The Implementation of an Evolvable Hardware System for Real Time Image Registration on a System-on-Chip Platform (Abstract)

J. R. Evans, University of Edinburgh

T. Arslan, University of Edinburgh

pp. 142

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Optimizing Signal Strength In-Situ Using an Evolvable Antenna System (Abstract)

Derek S. Linden, Linden Innovation Research

pp. 147

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Evolving Optimal Parameters for Swarm Control (PDF)

Jennifer Golbeck, University of Maryland at College Park

pp. 152

Coevolution of Form and Function in the Design of Micro Air Vehicles (Abstract)

Magdalena D. Bugajska, Naval Research Laboratory

Alan C. Schultz, Naval Research Laboratory

pp. 154

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5. New Avenues for Evolvable Hardware

Evolution in materio: Looking Beyond the Silicon Box (Abstract)

Julian F. Miller, University of Birmingham

Keith Downing, Norwegian University of Science and Technology

pp. 167

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Evolving Quantum Circuits Using Genetic Algorithm (Abstract)

Martin Lukac, Portland State University

Marek Perkowski, Portland State University

pp. 177

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Evolution of Quantum Algorithms for Computer of Reversible Operators (PDF)

Alvin J. Surkan, University of Nebraska at Lincoln

Amiran Khuskivadze, University of Nebraska at Lincoln

pp. 186

6. Cellular Automata

High-Performance Cellular Automata Random Number Generators for Embedded Probabilistic Computing Systems (Abstract)

Barry Shackleford, Hewlett-Packard Laboratories

Motoo Tanaka, Hewlett-Packard Laboratories

Richard J. Carter, Hewlett-Packard Laboratories

Greg Snider, Hewlett-Packard Laboratories

pp. 191

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Self-Reproduction in Asynchronous Cellular Automata (Abstract)

Chrystopher L. Nehaniv, University of Hertfordshire

pp. 201

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Evolving Cellular Automata to Model Fluid Flow in Porous Media (Abstract)

Tina Yu, ChevronTexaco Information Technology Company

Seong Lee, ChevronTexaco Exploration & Production Technology Company

pp. 210

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7. Embryonics and Bio-Inspired Architectures

The BioWall: An Electronic Tissue for Prototyping Bio-Inspired Systems (Abstract)

Gianluca Tempesti, Swiss Federal Institute of Technology in Lausanne

Daniel Mange, Swiss Federal Institute of Technology in Lausanne

André Stauffer, Swiss Federal Institute of Technology in Lausanne

Christof Teuscher, Swiss Federal Institute of Technology in Lausanne

pp. 221

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Implementing Asynchronous Embryonic Circuits using AARDVArc (Abstract)

Alexander H. Jackson, University of York

Andrew M. Tyrrell, University of York

pp. 231

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Towards Development in Evolvable Hardware (Abstract)

Timothy G. W. Gordon, University College London

Peter J. Bentley, University College London

pp. 241

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Circuit Morphologies and Ontogenies (Abstract)

R. Timothy Edwards, Johns Hopkins University

pp. 251

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An Immunochip Architecture and Its Emulation (Abstract)

Alexander Tarakanov, Russian Academy of Sciences

Dipankar Dasgupta, University of Memphis

pp. 261

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Towards an Artificial Neural Network Framework (Abstract)

Felix Schürmann, Heidelberg University

Steffen Hohmann, Heidelberg University

Johannes Schemmel, Heidelberg University

Karlheinz Meier, Heidelberg University

pp. 266

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Reversible Evolvable Networks: A Reversible Evolvable Boolean Network Architecture and Methodology to Overcome the Heat Generation Problem in Molecular Scale Brain Building (PDF)

Hugo de GARIS, Utah State University

Jonathan DINERSTEIN, Utah State University

Ravichandra SRIRAM, Utah State University

pp. 274

"TiPo" — A "Timed Pointer" Neural Net Model with Superior Evolvabilities for Implementation in a Second-Generation Brain-Building Machine BM2 (Abstract)

Jonathan Dinerstein, Sorenson Media, Inc.

Hugo de Garis, Utah State University

pp. 276

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Author Index

Author Index (PDF)

pp. 279