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The Second NASA/DoD Workshop on Evolvable Hardware (EH'00)
Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs
Palo Alto, California
July 13-July 15
ISBN: 0-7695-0762-X
| ASCII Text | x | ||
| Vesselin K. Vassilev, Julian F. Miller, "Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs," Evolvable Hardware, NASA/DoD Conference on, pp. 55, The Second NASA/DoD Workshop on Evolvable Hardware (EH'00), 2000. | |||
| BibTex | x | ||
| @article{ 10.1109/EH.2000.869342, author = {Vesselin K. Vassilev and Julian F. Miller}, title = {Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs}, journal ={Evolvable Hardware, NASA/DoD Conference on}, volume = {0}, year = {2000}, isbn = {0-7695-0762-X}, pages = {55}, doi = {http://doi.ieeecomputersociety.org/10.1109/EH.2000.869342}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Evolvable Hardware, NASA/DoD Conference on TI - Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs SN - 0-7695-0762-X SP EP A1 - Vesselin K. Vassilev, A1 - Julian F. Miller, PY - 2000 VL - 0 JA - Evolvable Hardware, NASA/DoD Conference on ER - | |||
A major problem in the evolutionary design of combinational circuits is the problem of scale. This refers to the design of electronic circuits in which the number of gates required to implement the optimal circuit is too high to search the space of all designs in reasonable time, even by evolution. The reason is twofold: firstly, the size of the search space becomes enormous as the number of gates required to implement the circuit is increased, and secondly, the time required to calculate the fitness of a circuit grows as the size of the truth table of the circuit.This paper studies the evolutionary design of combinational circuits, particularly the three-bit multiplier circuit, in which the basic building blocks are small sub-circuits, modules inferred from other evolved designs. The structure of the resulting fitness landscapes is studied and it is shown that in general the principles of evolving digital circuits are scalable. Thus to evolve digital circuits using modules is faster, since the building blocks of the circuit are sub-circuits rather than two-input gates. This can also be a disadvantage, since the number of gates of the evolved designs grows as the size of the modules used.
Citation:
Vesselin K. Vassilev, Julian F. Miller, "Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs," eh, pp.55, The Second NASA/DoD Workshop on Evolvable Hardware (EH'00), 2000
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