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1997 European Design and Test Conference (ED&TC '97)
March 17-March 20
ISBN: 0-8186-7786-4
Table of Contents
Session 1A: System Analysis Techniques and Applications
System Analysis Techniques and Applications
Ali Dasdan, Dept. of Comp. Sci., Univ. of Illinois, IL, USA
Anmol Mathur, Silicon Graphics Inc., Mountain View, CA, USA
Rajesh K. Gupta, Dept. of Info. & Comp. Sci., Univ. of California, Irvine, CA, USA
pp. 2
Preeti Ranjan Panda, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Nikil D. Dutt, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Alexandru Nicolau, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 7
Session 1B: Sequential ATPG
Sequential ATPG
Michael S. Hsiao, University of Illinois, Illinois, USA
Elizabeth M. Rudnick, University of Illinois, Illinois, USA
Janak H. Patel, University of Illinois, Illinois, USA
pp. 22
A. Dargelas, Univ. Montpellier II / CNRS, Montpellier, FRANCE
C. Gauthron, COMPASS Design Automation, Sophia-Antipolis, FRANCE
Y. Bertrand, Univ. Montpellier II / CNRS, Montpellier, FRANCE
pp. 29
F. Corno, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Rebaudengo, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 37
Session 1C: Design and Design Methodology for Analog Circuits
Design and Design Methodology for Analog Circuits
Philippe Benabes, Ecole Superieure d'Electr., Gif-sur-Yvette, France
Mansour Keramat, Ecole Superieure d'Electr., Gif-sur-Yvette, France
Richard Kielbasa, Ecole Superieure d'Electr., Gif-sur-Yvette, France
pp. 46
Guo-Neng Lu, Universit? Pierre et Marie Curie ( PARIS VI )
Gerard Sou, Universit? Pierre et Marie Curie ( PARIS VI )
pp. 51
S. Donnay, Katholieke Universiteit Leuven, Heverlee, Belgium
G. Gielen, Katholieke Universiteit Leuven, Heverlee, Belgium
W. Sansen, Katholieke Universiteit Leuven, Heverlee, Belgium
W. Kruiskamp, Eindhoven University of Technology, Eindhoven, The Netherlands
D. Leenaerts, Eindhoven University of Technology, Eindhoven, The Netherlands
W. Van Bokhoven, Eindhoven University of Technology, Eindhoven, The Netherlands
pp. 56
Session 2A: Panel P1
How to Introduce Advanced Design Technology in Qualified Industrial Design Flows?
Session 2B: Advances in Built-In Self-Test
Advances in Built-In Self-Test
M. Nourani, Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
C. Papachristou, Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
pp. 64
Dimitrios Kagaris, Electrical Engineering Dept., Southern Illinois University, IL, USA
Spyros Tragoudas, Computer Science Dept., Southern Illinois University, IL, USA
pp. 77
Session 2C: Synthesis of Controllers
Synthesis of Controllers
Kazuo Iwama, Dept of Computer Science & Communication Engineering, Kyushu University, Japan
Sunao Sawada, Dept of Computer Science & Communication Engineering, Kyushu University, Japan
Kensuke Hino, Industria1 Instrumentation & Control Systems Department, TOSHIBA Corporation, Japan
Hiroyuki Kurokawa, Research & Development, JUSTSYSTEM Corporation, Japan
pp. 90
Jordi Cortadella, Universit Politecnica de Catalunya, Barcelona, Spain
Michael Kishinevsky, The University of Aizu, Aizu- Wakamatsu, Japan
Alex Kondratyev, The University of Aizu, Aizu- Wakamatsu, Japan
Luciano Lavagno, Politecnico di Torino, Torino, Italy
Alex Yakovlev, University of Newcastle upon Tyne, England
pp. 98
Session 2D: Microsystems Design I
Microsystems Design I
Klaus Hofmann, Darmstadt University of Technology, Institute of Microelectronic Systems, Darmstadt, Germany
Manfred Glesner, Darmstadt University of Technology, Institute of Microelectronic Systems, Darmstadt, Germany
Nicu Sebe, University Bucharest, Romania
A. Manolescu, University Bucharest, Romania
Santiago Marco, University of Barcelona, Spain
Josep Samitier, University of Barcelona, Spain
Jean-Michel Karam, INPG / TIMA, Grenoble, France
Bernard Courtois, INPG / TIMA, Grenoble, France
pp. 108
W. Wünsche, Fraunhofer-Inst. for Integrated Circuits, Dresden, Germany
C. Clauß, Fraunhofer-Inst. for Integrated Circuits, Dresden, Germany
P. Schwarz, Fraunhofer-Inst. for Integrated Circuits, Dresden, Germany
F. Winkler, Fraunhofer-Inst. for Integrated Circuits, Dresden, Germany
pp. 113
B. Romanowicz, Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
M. Laudon, Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
P. Lerch, Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
P. Renaud, Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
H.P. Amann, Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
A. Boegli, Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
V. Moser, Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
F. Pellandini, Inst. of Microsyst., Swiss Federal Inst. of Technol., Lausanne, Switzerland
pp. 119
Session 3A: Software Generation for Embedded Processors
Software Generation for Embedded Processors
M.L.G. Smeets, Philips Res., Eindhoven, Netherlands
E.H.L. Aarts, Philips Res., Eindhoven, Netherlands
G. Essink, Philips Res., Eindhoven, Netherlands
E.A. de Kock, Philips Res., Eindhoven, Netherlands
pp. 126
Yanbing Li, Dept. of Electr. Eng., Princeton University, NJ, USA
Wayne Wolf, Dept. of Electr. Eng., Princeton University, NJ, USA
pp. 134
Rainer Leupers, University of Dortmund, Dortmund, Germany
Peter Marwedel, University of Dortmund, Dortmund, Germany
pp. 140
Session 3B: Register Transfer Level Test Synthesis
Register Transfer Level Test Synthesis
Subhrajit Bhattacharya, C&C Res. Labs., NEC USA, Princeton, NJ, USA
Sujit Dey, C&C Res. Labs., NEC USA, Princeton, NJ, USA
Bhaskar Sengupta, C&C Res. Labs., NEC USA, Princeton, NJ, USA
pp. 146
Xinli Gu, Synopsys, Inc., Mountain View, CA, USA
Erik Larsson, Dept. of Comp. and Info. Sci., Link?ping University, Link?ping, Sweden
Krzysztof Kuchinski, Dept. of Comp. and Info. Sci., Link?ping University, Link?ping, Sweden
Zebo Peng, Dept. of Comp. and Info. Sci., Link?ping University, Link?ping, Sweden
pp. 153
M.L. Flottes, Lab. d'Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, Franc
R. Pires, Lab. d'Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, Franc
B. Rouzeyre, Lab. d'Inf., de Robotique et de Microelectron., Univ. des Sci. et Tech. du Languedoc, Montpellier, Franc
pp. 158
Session 3C: BDD's and Formal Verification
BDD's and Formal Verification
A. Hett, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
R. Drechsler, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
B. Becker, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 168
G. Cabodi, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Camurati, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
L. Lavagno, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
S. Quer, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 176
T. Kropf, Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
J. Ruf, Inst. of Comput. Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 182
Session 3D: Microsystems Design II
Microsystems Design II
J.P. Fradin, Epsilon Ingenierie, Labege, France
L. Molla, Epsilon Ingenierie, Labege, France
B. Desaunettes, Epsilon Ingenierie, Labege, France
pp. 190
R.J.W.T. Tangelder, MESA Res. Inst., Twente Univ., Enschede, Netherlands
G. Diemel, MESA Res. Inst., Twente Univ., Enschede, Netherlands
H.G. Kerkhoff, MESA Res. Inst., Twente Univ., Enschede, Netherlands
pp. 195
M. Lang, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
D. David, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
M. Glesner, Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
pp. 200
Session 4A: Panel P3
What Will Be the Right Test Methodology for the Year 2005?
Session 4B: High Performance Architectures for Multimedia and Communication ASICs
High Performance Architectures for Multimedia and Communication ASICs
Ander Royo, Universidad Polit?cnica de Madrid
Javier Moran, Universidad Polit?cnica de Madrid
Juan Carlos Lopez, Universidad Polit?cnica de Madrid
pp. 213
J. Riesco, Telefonica Investigacion y Desarrollo, Madrid, Spain
J.C. Díaz, Telefonica Investigacion y Desarrollo, Madrid, Spain
L.A. Merayo, Telefonica Investigacion y Desarrollo, Madrid, Spain
J.L. Conesa, Telefonica Investigacion y Desarrollo, Madrid, Spain
C. Santos, Telefonica Investigacion y Desarrollo, Madrid, Spain
E. Juárez, Telefonica Investigacion y Desarrollo, Madrid, Spain
pp. 218
Session 4C: Decision Diagrams and Diagnosis
Decision Diagrams and Diagnosis
C. Scholl, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
S. Melchior, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
G. Hotz, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
P. Molitor, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 229
Session 4D: Performance Modeling
Performance Modeling
J.P. Fishburn, Lucent Technol., AT&T Bell Labs., Murray Hill, NJ, USA
pp. 244
S. Kundu, Res. Lab., IBM Corp., Austin, TX, USA
U. Ghoshal, Res. Lab., IBM Corp., Austin, TX, USA
pp. 252
Session 5A: Hot Topic HT1
Session 5B: Progress in IDDQ Test Technology
Progress in IDDQ Test Technology
V. Stopjaková, Dept. of Microelectron., Slovak Tech. Univ., Bratislava, Slovakia
H. Manhaeve, Dept. of Microelectron., Slovak Tech. Univ., Bratislava, Slovakia
pp. 266
Session 5C: Architecture Exploration
Architecture Exploration
Pradip K. Jha, IBM East Fishkill Facility
Nikil D. Dutt, University of California at Irvine
pp. 288
Min Xu, University of California, Irvine
Fadi Kurdahi, University of California, Irvine
pp. 299
Session 5D: Layout Design
Layout Design
K.S. Seong, Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
C.M. Kyung, Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Taejon, South Korea
pp. 306
Le-Chin Eugene Liu, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C. Sechen, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 311
Hsiao-Ping Tseng, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
C. Sechen, Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
pp. 319
Session 6A: Hot Topic HT2
Session 6B: Testability Solutions for Regular Structures
Testability Solutions for Regular Stuctures
R.O. Duarte, TIMA, Grenoble, France
M. Nicolaidis, TIMA, Grenoble, France
H. Bederr, TIMA, Grenoble, France
Y. Zorian, TIMA, Grenoble, France
pp. 335
Session 6C: Data Converter Test Issues
Data Converter Test Issues
K. Arabi, Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
B. Kaminska, Dept. of Electr. & Comput. Eng., Ecole Polytech., Montreal, Que., Canada
pp. 348
R. de Vries, Philips Res. Lab., Eindhoven, Netherlands
T. Zwemstra, Philips Res. Lab., Eindhoven, Netherlands
E.M.J.G. Bruls, Philips Res. Lab., Eindhoven, Netherlands
P.P.L. Regtien, Philips Res. Lab., Eindhoven, Netherlands
pp. 353
E.K.F. Lee, Dept. of Electr. Eng. & Comput. Eng., Iowa State Univ., Ames, IA, USA
pp. 359
Session 7A: Hot Topic HT3
Session 7B: Extensions and Acceleration of Discrete Event Simulation
Extensions and Acceleration of Discrete Event Simulation
P. Walker, Div. of Eng., Brown Univ., Providence, RI, USA
S. Ghosh, Div. of Eng., Brown Univ., Providence, RI, USA
pp. 368
P. Walker, Div. of Eng., Brown Univ., Providence, RI, USA
S. Ghosh, Div. of Eng., Brown Univ., Providence, RI, USA
pp. 378
Session 7C: Analog Design and Layout Tools
Analog Design and Layout Tools
L.T. Walczowski, Electron. Eng. Labs., Kent Univ., Canterbury, UK
D. Nalbantis, Electron. Eng. Labs., Kent Univ., Canterbury, UK
W.A.J. Waller, Electron. Eng. Labs., Kent Univ., Canterbury, UK
K. Shi, Electron. Eng. Labs., Kent Univ., Canterbury, UK
pp. 384
Juan A. Prieto, Centro Nacional de Microelectronica.
Adoracion Rueda, Centro Nacional de Microelectronica.
Jose M. Quintana, Centro Nacional de Microelectronica.
Jose L. Huertas, Centro Nacional de Microelectronica.
pp. 389
Ignacio Garcia-Vargas, Centro Nacional de Microelectronica
Mariano Galan, Centro Nacional de Microelectronica
Francisco V. Fernandez, Centro Nacional de Microelectronica
Angel Rodriguez-Vazque., Centro Nacional de Microelectronica
pp. 395
Session 8A: Embedded Tutorial
Hardware and Software Co-Design in Europe and the USA - A Collaborative Initiative
Session 8B: Power Modeling and Estimation
Power Modeling and Estimation
A. Bogliolo, DEIS, Bologna Univ., Italy
L. Benini, DEIS, Bologna Univ., Italy
G. De Micheli, DEIS, Bologna Univ., Italy
pp. 404
S. Gavrilov, Acad. of Sci., Moscow, Russia
A. Glebov, Acad. of Sci., Moscow, Russia
S. Rusakov, Acad. of Sci., Moscow, Russia
D. Blaauw, Acad. of Sci., Moscow, Russia
L. Jones, Acad. of Sci., Moscow, Russia
G. Vijayan, Acad. of Sci., Moscow, Russia
pp. 411
Vikram Saxena, Synopsys Inc.
Farid N. Najm, University of Illinois at Urbana-Champaign
Ibrahim Hajj, University of Illinois at Urbana-Champaign
pp. 416
Session 8C: Formal Methods in Synthesis and Verification
Formal Methods in Synthesis and Verification
S. Chiusano, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
F. Corno, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 422
D. Eisenbiegler, Inst. for Circuit Design & Fault Tolerance, Karlsruhe Univ., Germany
R. Kumar, Inst. for Circuit Design & Fault Tolerance, Karlsruhe Univ., Germany
C. Blumenrohr, Inst. for Circuit Design & Fault Tolerance, Karlsruhe Univ., Germany
pp. 427
S. Hendriex, Katholieke Univ., Leuven, Heverlee, Belgium
L. Claesen, Katholieke Univ., Leuven, Heverlee, Belgium
pp. 432
Session 9A: Panel P2
Are There Conflicts of Interest in Intellectual Property Based Business?
Session 9B: Concurrent Checking
Concurrent Checking
M. Favalli, DEIS, Bologna Univ., Italy
C. Metra, DEIS, Bologna Univ., Italy
pp. 445
Session 9C: New Ideas in Scheduling
New Ideas in Scheduling
Dirk Herrmann, Technical University of Braunschweig
Rolf Ernst, Technical University of Braunschweig
pp. 463
W.F.J. Verhaegh, Philips Res. Lab., Eindhoven, Netherlands
P.E.R. Lippens, Philips Res. Lab., Eindhoven, Netherlands
E.H.L. Aarts, Philips Res. Lab., Eindhoven, Netherlands
J.L. van Meerbergen, Philips Res. Lab., Eindhoven, Netherlands
pp. 468
Session 10A: System Level Design Representation and Transformation
System Level Design Representation and Transformation
T. Grotker, Aachen Univ. of Technol., Germany
R. Schoenen, Aachen Univ. of Technol., Germany
H. Meyr, Aachen Univ. of Technol., Germany
pp. 482
Session 10B: Diagnosis and Test Generation
Diagnosis and Test Generation
S. Narayanan, Sun Microsyst. Inc., Mountain View, CA, USA
R. Srinivasan, Sun Microsyst. Inc., Mountain View, CA, USA
R.P. Kunda, Sun Microsyst. Inc., Mountain View, CA, USA
M.E. Levitt, Sun Microsyst. Inc., Mountain View, CA, USA
S. Bozorgui-Nesbat, Sun Microsyst. Inc., Mountain View, CA, USA
pp. 494
J.T. de Sousa, Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
P.Y.K. Cheung, Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK
pp. 501
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, US
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, US
pp. 506
Session 10C: Logic Synthesis for Low Power
Logic Synthesis for Low Power
L. Benini, Comput. Syst. Lab., Stanford Univ., CA, USA
G. De Micheli, Comput. Syst. Lab., Stanford Univ., CA, USA
E. Macii, Comput. Syst. Lab., Stanford Univ., CA, USA
M. Poncino, Comput. Syst. Lab., Stanford Univ., CA, USA
R. Scarsi, Comput. Syst. Lab., Stanford Univ., CA, USA
pp. 514
P. Surti, Intel Corp., Folsom, CA, USA
L.F. Chao, Intel Corp., Folsom, CA, USA
A. Tyagi, Intel Corp., Folsom, CA, USA
pp. 521
Session 11A: System Design Methodologies
Synthesis Design Methodologies
I. Gibson, Canon Inf. Syst. Res., North Ryde, NSW, Australia
C. Amies, Canon Inf. Syst. Res., North Ryde, NSW, Australia
pp. 532
Session 11B: Testability at Different Abstraction Levels
Testability at Different Abstraction Levels
R. Drechsler, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
H. Hengster, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
H. Schafer, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
J. Hartmann, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
B. Becker, Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
pp. 548
I. Pomeranz, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
S.M. Reddy, Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
pp. 554
A. Benso, Politecnico di Torino, Italy
P. Prinetto, Politecnico di Torino, Italy
M. Rebaudengo, Politecnico di Torino, Italy
M. Sonza Reorda, Politecnico di Torino, Italy
R. Ubar, Politecnico di Torino, Italy
pp. 560
Session 11C: Hardware and Software Tools for Analog and Mixed-Signal Test
Hardware and Software Tools for Analog and Mixed-Signal Test
M. Renovell, Lab. d'Inf., LIRMM, Montpellier, France
F. Azais, Lab. d'Inf., LIRMM, Montpellier, France
Y. Bertrand, Lab. d'Inf., LIRMM, Montpellier, France
pp. 568
V. Kaal, MESA Res. Inst., Twente Univ., Enschede, Netherlands
H. Kerkhoff, MESA Res. Inst., Twente Univ., Enschede, Netherlands
pp. 581
Session 11D: Power Estimation and Modeling
Power Estimation and Modeling
J.E. Crenshaw, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
M. Sarrafzadeh, Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
pp. 590
S. Manich, Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 597
S. Turgis, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
J.M. Daga, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
J.M. Portal, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
D. Auvergne, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 603
Poster Session
J. Faura, SIDSA, Parque Technol., Madrid, Spain
C. Horton, SIDSA, Parque Technol., Madrid, Spain
B. Krah, SIDSA, Parque Technol., Madrid, Spain
J. Cabestany, SIDSA, Parque Technol., Madrid, Spain
M.A. Aguirre, SIDSA, Parque Technol., Madrid, Spain
J.M. Insenser, SIDSA, Parque Technol., Madrid, Spain
pp. 610
J.A.J. Leijten, Philips Res. Lab., Eindhoven, Netherlands
J.L. van Meerbergen, Philips Res. Lab., Eindhoven, Netherlands
A.H. Timmer, Philips Res. Lab., Eindhoven, Netherlands
J.A.G. Jess, Philips Res. Lab., Eindhoven, Netherlands
pp. 611
C. Liem, Lab. TIMA, INPG, Grenoble, France
P. Paulin, Lab. TIMA, INPG, Grenoble, France
A. Jerraya, Lab. TIMA, INPG, Grenoble, France
pp. 612
T. Rowekamp, German Nat. Res. Center for Comput. Sci., St. Augustin, Germany
L. Peters, German Nat. Res. Center for Comput. Sci., St. Augustin, Germany
pp. 613
H. Ihs, Lab. d'Inf., Robotique et de Micro-electronique, Montpellier, France
C. Dufaza, Lab. d'Inf., Robotique et de Micro-electronique, Montpellier, France
pp. 616
V. Szekely, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
A. Pahi, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
A. Poppe, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
M. Rencz, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
A. Csendes, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
pp. 617
I. Ozimek, Institute Jozef Stefan
R. Verlic, Institute Jozef Stefan
J. Tasic, University of Ljubljana
pp. 620
A. Mignotte, Ecole Normale Superieure de Lyon, France
O. Peyran, Ecole Normale Superieure de Lyon, France
pp. 621
J. Walrath, Dept. of Electron. Comput., Cincinnati Univ., OH, USA
R. Vemuri, Dept. of Electron. Comput., Cincinnati Univ., OH, USA
W. Bradley, Dept. of Electron. Comput., Cincinnati Univ., OH, USA
pp. 622
A. Ursu, Technical University of Moldova
G. Gruita, Technical University of Moldova
S. Zaporojan, Technical University of Moldova
pp. 623
M. Wolf, Otto-von-Guericke-Univ., Magdeburg, Germany
U. Kleine, Otto-von-Guericke-Univ., Magdeburg, Germany
pp. 624
M.F. Abdulla, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
C.P. Ravikumar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
A. Kumar, Dept. of Comput. Sci. & Eng., Indian Inst. of Technol., New Delhi, India
pp. 625
A.J. van de Goor, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
G.N. Gaydadjiev, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
V.N. Yarmolik, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
V.G. Mikitjuk, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 627
R.D. Blanton, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J.P. Hayes, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 628
M. Svajda, Tech. Univ. of Brno, Czech Republic
B. Straka, Tech. Univ. of Brno, Czech Republic
H. Manhaeve, Tech. Univ. of Brno, Czech Republic
pp. 629
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