Classical strategies in design for testability are applied at the gate-level, after the RT-logic synthesis process. New techniques covering test and synthesis (Test Synthesis) are appearing but their application is mainly oriented to gate level (commercial tools such as Synopsys). On the other hand, most high-level synthesis tools do not take into account the testability of the final architecture. This paper presents a high-level synthesis system which includes testability improvement among its goals. The aforementioned system generates loop free circuits and are, therefore, easily testable with partial scan techniques. In order to achieve this, a complete RT-level loop classification is made and the origin at the algorithmic level is analyzed in order to avoid loops during the synthesis process, not only in the data path but also in the controller. With the usual high-level synthesis benchmarks, the proposed system reaches 100% fault coverages with a smaller area than other high-level synthesis tools.