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1996 European Design and Test Conference (ED&TC '96)
High Rate Soft Output Viterbi Decoder
Paris, FRANCE
March 11-March 14
ISBN: 0-8186-7423-7
| ASCII Text | x | ||
| Eric Luthi, Emmanuel Casseau, "High Rate Soft Output Viterbi Decoder," European Design and Test Conference, pp. 315, 1996 European Design and Test Conference (ED&TC '96), 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/EDTC.1996.494319, author = {Eric Luthi and Emmanuel Casseau}, title = {High Rate Soft Output Viterbi Decoder}, journal ={European Design and Test Conference}, volume = {0}, year = {1996}, issn = {1066-1409}, pages = {315}, doi = {http://doi.ieeecomputersociety.org/10.1109/EDTC.1996.494319}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - European Design and Test Conference TI - High Rate Soft Output Viterbi Decoder SN - 1066-1409 SP EP A1 - Eric Luthi, A1 - Emmanuel Casseau, PY - 1996 KW - digital communication systems KW - high data rates KW - Viterbi decoding KW - soft output Viterbi decoding KW - collapsed trellis KW - VLSI design VL - 0 JA - European Design and Test Conference ER - | |||
This paper presents the architecture of a high rate soft output Viterbi decoder (100 Mb/s for worst case process conditions, 8 states, coding rate R=1/2, using a 0.6ym CMOS technology), using the "radix" trellis method (collapsed trellis) to speed up the rate of a soft output decoder using the Viterbi algorithm and the a posteriori weighting algorithm. The size of this circuit is roughly twice that of the original soft output Viterbi decoder while the speed is increased by a factor of 2. Because of its performances, this circuit is very attractive for satellite digital communication systems and is at the root of "turbo-codes", which are a new class of convolutional codes whose performances, in terms of bit error rate, are close to the Shannon limit.
Index Terms:
digital communication systems, high data rates, Viterbi decoding, soft output Viterbi decoding, collapsed trellis, VLSI design
Citation:
Eric Luthi, Emmanuel Casseau, "High Rate Soft Output Viterbi Decoder," edtc, pp.315, 1996 European Design and Test Conference (ED&TC '96), 1996
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