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1996 European Design and Test Conference (ED&TC '96)
Design and selection of buffers for minimum power-delay product
Paris, FRANCE
March 11-March 14
ISBN: 0-8186-7423-7
| ASCII Text | x | ||
| S. Turgis, N. Azemard, D. Auvergne, "Design and selection of buffers for minimum power-delay product," European Design and Test Conference, pp. 224, 1996 European Design and Test Conference (ED&TC '96), 1996. | |||
| BibTex | x | ||
| @article{ 10.1109/EDTC.1996.494153, author = {S. Turgis and N. Azemard and D. Auvergne}, title = {Design and selection of buffers for minimum power-delay product}, journal ={European Design and Test Conference}, volume = {0}, year = {1996}, issn = {1066-1409}, pages = {224}, doi = {http://doi.ieeecomputersociety.org/10.1109/EDTC.1996.494153}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - European Design and Test Conference TI - Design and selection of buffers for minimum power-delay product SN - 1066-1409 SP EP A1 - S. Turgis, A1 - N. Azemard, A1 - D. Auvergne, PY - 1996 KW - CMOS logic circuits; delays; logic design; integrated circuit design; buffer circuits; buffer design; buffer selection; minimum power-delay product; explicit delay modeling; CMOS buffers; power dissipation; buffer insertion limit; SPICE simulations; two stage inverter arrays; standard cell library VL - 0 JA - European Design and Test Conference ER - | |||
Using explicit modeling of delays, we present and discuss real design conditions of CMOS buffers from the viewpoint of power dissipation. Efficiency of buffer implementation is first studied through the definition of limit for buffer insertion. Closed form alternatives to the design for minimum power-delay product are then proposed in terms of this limit. Validations are obtained through SPICE simulations on two stage inverter arrays. Applications are given to a standard cell library in comparing implementations for different selection alternatives.
Index Terms:
CMOS logic circuits; delays; logic design; integrated circuit design; buffer circuits; buffer design; buffer selection; minimum power-delay product; explicit delay modeling; CMOS buffers; power dissipation; buffer insertion limit; SPICE simulations; two stage inverter arrays; standard cell library
Citation:
S. Turgis, N. Azemard, D. Auvergne, "Design and selection of buffers for minimum power-delay product," edtc, pp.224, 1996 European Design and Test Conference (ED&TC '96), 1996
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