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1995 European Design and Test Conference (ED&TC '95)
Paris, France
March 06-March 09
ISBN: 0-8186-7039-8
Table of Contents
Session 1A: DSP and Multimedia
DSP and Multimedia
M. Kovac, Fac. of Electr. Eng., Zagreb Univ., Croatia
N. Ranganathan, Fac. of Electr. Eng., Zagreb Univ., Croatia
M. Zagar, Fac. of Electr. Eng., Zagreb Univ., Croatia
pp. 2
J.-M. Bourguet, Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
T. Nancy, Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
S.J. Wei, Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
J. Leroy, Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
R.G. Crappe, Lab. of Microelectron., Faculte Polytech. de Mons, Belgium
pp. 7
G. Knittel, WSI/GRIS, Tubingen Univ., Germany
A. Schilling, WSI/GRIS, Tubingen Univ., Germany
pp. 12
Session 1B: Mixed-Signal DFT
Mixed-Signal DFT
F.C.M. Kuijstermans, Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
M. Sachdev, Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
A.P. Thijssen, Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 18
A.H. Bratt, Dept. of Eng., Lancaster Univ., UK
A.M.D. Richardson, Dept. of Eng., Lancaster Univ., UK
R.J.A. Harvey, Dept. of Eng., Lancaster Univ., UK
A.P. Dorey, Dept. of Eng., Lancaster Univ., UK
pp. 24
M. Lubaszewski, DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
V. Kolarik, DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
S. Mir, DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
C. Nielsen, DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
B. Courtois, DELET, Univ. Federal do Rio Grande do Sul, Porto Alegre, Brazil
pp. 34
Session 1C: Exact Methods in Architectural Timing Optimization
Exact Methods in Architectural Timing Optimization
A.H. Timmer, Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
J.A.G. Jess, Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
pp. 42
I. Radivojevic, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
F. Brewer, Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
pp. 48
N.L. Passos, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
E.H.-M. Sha, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
Liang-Fang Chao, Dept. of Comput. Sci. & Eng., Notre Dame Univ., IN, USA
pp. 54
Session 2A: Circuit Partitioning
Circuit Partitioning
D.J.-H. Huang, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
A.B. Kahng, Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
pp. 60
Honghua Yang, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D.F. Wong, Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 65
B.M. Riess, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
A.A. Schoene, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 71
Panel Session 2B
ATE Is Dead-Long Live Automated Test
Session 2C: Combinational Logic Synthesis
Combinational Logic Synthesis
A. Bogliolo, Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
M. Damiani, Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 80
R. Drechsler, Dept. of Comput. Sci., Frankfurt Univ., Germany
B. Becker, Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 91
Session 3A: Designs and Tools for Analogue and Mixed Signal ICs
Designs and Tools for Analogue and Mixed Signal ICs
Nianxiong Tan, Dept. of Electr. Eng., Linkoping Univ., Sweden
S. Eriksson, Dept. of Electr. Eng., Linkoping Univ., Sweden
pp. 100
A. Pletersek, Microelectron. Lab., Ljubljana Univ., Slovenia
D. Strle, Microelectron. Lab., Ljubljana Univ., Slovenia
J. Trontelj, Microelectron. Lab., Ljubljana Univ., Slovenia
pp. 105
K. Hayat-Dawoodi, Austria Mikro Syst. Int. AG, Unterpremstatten, Austria
O. Alminde, Austria Mikro Syst. Int. AG, Unterpremstatten, Austria
V. Kunc, Austria Mikro Syst. Int. AG, Unterpremstatten, Austria
M. Pauritsch, Austria Mikro Syst. Int. AG, Unterpremstatten, Austria
pp. 113
P. Veselinovic, Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
D. Leenaerts, Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
W. van Bokhoven, Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
F. Leyn, Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
F. Proesmans, Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
G. Gielen, Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
W. Sansen, Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
pp. 119
Session 3B: Memory Testing
Memory Testing
M.G. Karpovsky, Boston Univ., MA, USA
A.J. van de Goor, Boston Univ., MA, USA
V.N. Yarmolik, Boston Univ., MA, USA
pp. 126
A.J. van de Goor, Delft Univ. of Technol., Netherlands
I. Schanstra, Delft Univ. of Technol., Netherlands
Y. Zorian, Delft Univ. of Technol., Netherlands
pp. 133
R.D. Adams, Microelectron. Div., IBM Corp., Essex Junction, VT, USA
J. Connor, Microelectron. Div., IBM Corp., Essex Junction, VT, USA
G.S. Koch, Microelectron. Div., IBM Corp., Essex Junction, VT, USA
L. Ternullo, Jr., Microelectron. Div., IBM Corp., Essex Junction, VT, USA
pp. 139
Session 3C: Sequential Logic Synthesis
Sequential Logic Synthesis
B. Lin, IMEC, Leuven, Belgium
G. de Jong, IMEC, Leuven, Belgium
T. Kolks, IMEC, Leuven, Belgium
pp. 144
L. Stok, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
I. Spillinger, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
G. Even, IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 150
Z. Hasan, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
M.J. Ciesielski, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 155
Session 4A: High Speed Telecom Design
High Speed Telecom Design
P. Plaza, Telefonica Investigacion y Desarrollo, Madrid, Spain
J.C. Diaz, Telefonica Investigacion y Desarrollo, Madrid, Spain
F. Calvo, Telefonica Investigacion y Desarrollo, Madrid, Spain
L. Merayo, Telefonica Investigacion y Desarrollo, Madrid, Spain
M. Zamboni, Telefonica Investigacion y Desarrollo, Madrid, Spain
P. Scarfone, Telefonica Investigacion y Desarrollo, Madrid, Spain
M. Barbini, Telefonica Investigacion y Desarrollo, Madrid, Spain
pp. 162
A. Onozawa, NTT LSI Labs., Atsugi, Japan
H. Kitazawa, NTT LSI Labs., Atsugi, Japan
K. Kawai, NTT LSI Labs., Atsugi, Japan
pp. 167
M. Diaz Nava, SGS-Thomson, Crolles, France
D. Belot, SGS-Thomson, Crolles, France
P. Delerue, SGS-Thomson, Crolles, France
J. Bulone, SGS-Thomson, Crolles, France
pp. 173
Session 4B: System Synthesis
System Synthesis
C.A. Valderrama, Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
A. Changuel, Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
P.V. Raghavan, Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
M. Abid, Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
T. Ben Ismail, Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
A.A. Jerraya, Syst. Level Synthesis Group, Inst. Nat. Polytech. de Grenoble, France
pp. 180
F. Vahid, Dept. of Comput. Sci., California Univ., Riverside, CA, USA
D.D. Gajski, Dept. of Comput. Sci., California Univ., Riverside, CA, USA
pp. 185
Session 4C: Advanced DFT Techniques
Advanced DFT Techniques
M.L. Flottes, Lab. d'Inf., de Robotique et de Microelectron., CNRS, Montpellier, France
D. Hammad, Lab. d'Inf., de Robotique et de Microelectron., CNRS, Montpellier, France
B. Rouzeyre, Lab. d'Inf., de Robotique et de Microelectron., CNRS, Montpellier, France
pp. 198
F. Fummi, Dipartimento di Elettronica, Politecnico di Milano, Italy
D. Sciuto, Dipartimento di Elettronica, Politecnico di Milano, Italy
M. Serra, Dipartimento di Elettronica, Politecnico di Milano, Italy
pp. 207
Li-Ren Huang, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Sy-Yen Kuo, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Ing-Yi Chen, Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
pp. 212
Session 5A: Digital and System Simulation
Digital and System Simulation
F. Pichon, RGS Div., Thomson-CSF, Gennesvilliers, France
S. Blanc, RGS Div., Thomson-CSF, Gennesvilliers, France
B. Candaele, RGS Div., Thomson-CSF, Gennesvilliers, France
pp. 218
J.W.G. Fleurkens, Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
C.A.J. van Eijk, Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
J.A.G. Jess, Design Autom. Sect., Eindhoven Univ. of Technol., Netherlands
pp. 223
Ing-Yi Chen, Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Geng-Lin Chen, Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Sy-Yen Kuo, Dept. of Electron. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
pp. 228
Session 5B: Code Generation
Code Generation
R. Leupers, Dept. of Comput. Sci., Dortmund Univ., Germany
P. Marwedel, Dept. of Comput. Sci., Dortmund Univ., Germany
pp. 239
M. Strik, Philips Res. Lab., Eindhoven, Netherlands
J. van Meerbergen, Philips Res. Lab., Eindhoven, Netherlands
A. Timmer, Philips Res. Lab., Eindhoven, Netherlands
J. Jess, Philips Res. Lab., Eindhoven, Netherlands
S. Note, Philips Res. Lab., Eindhoven, Netherlands
pp. 244
Session 5C: Sequential ATPG and Diagnosis
Sequential ATPG and Diagnosis
T.E. Marchok, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
A. El-Maleh, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
J. Rajski, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 252
Jaehong Park, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Chanhee Oh, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M.R. Mercer, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 262
F. Corno, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Rebaudengo, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 267
Session 6A: CAD Frameworks
CAD Frameworks
Y. Mathys, Semicond. Syst. Design Technol., Motorola Inc., USA
M. Morgan, Semicond. Syst. Design Technol., Motorola Inc., USA
S. Soudagar, Semicond. Syst. Design Technol., Motorola Inc., USA
pp. 274
E. Kwee-Christoph, Comput. Sci. Res. Center, Forschungszentrum Inf., Karlsruhe, Germany
F. Feldbusch, Comput. Sci. Res. Center, Forschungszentrum Inf., Karlsruhe, Germany
R. Kumar, Comput. Sci. Res. Center, Forschungszentrum Inf., Karlsruhe, Germany
A. Kunzmann, Comput. Sci. Res. Center, Forschungszentrum Inf., Karlsruhe, Germany
pp. 280
A. Kunzmann, Forschungszentrum Inf., Karlsruhe, Germany
R. Seepold, Forschungszentrum Inf., Karlsruhe, Germany
pp. 285
Panel Session 6B
Simulation Versus Formal Verification
Session 6C: Test Generation and Testability
Test Generation and Testability
L.-C. Wang, Texas Univ., Austin, TX, USA
M.R. Mercer, Texas Univ., Austin, TX, USA
T.W. Williams, Texas Univ., Austin, TX, USA
pp. 294
M.H.C. Lee, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
D.L. Tao, Dept. of Electr. Eng., State Univ. of New York, Stony Brook, NY, USA
pp. 303
G. Van Brakel, MESA Res. Inst., Twente Univ., Enschede, Netherlands
U. Glaser, MESA Res. Inst., Twente Univ., Enschede, Netherlands
H.G. Kerkhoff, MESA Res. Inst., Twente Univ., Enschede, Netherlands
H.T. Vierhaus, MESA Res. Inst., Twente Univ., Enschede, Netherlands
pp. 308
Session 7A: Applications of Symbolic Traversal Techniques
Applications of Symbolic Traversal Techniques
J. Frossl, Inst. fur Rechnerentwurf und Fehlertoleranz, Karlsruhe Univ., Germany
T. Kropf, Inst. fur Rechnerentwurf und Fehlertoleranz, Karlsruhe Univ., Germany
pp. 314
F. Corno, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Sonza Reorda, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 320
A. Kondratyev, Aizu Univ., Aizu-Wakamatsu, Japan
J. Cortadella, Aizu Univ., Aizu-Wakamatsu, Japan
M. Kishinevsky, Aizu Univ., Aizu-Wakamatsu, Japan
E. Pastor, Aizu Univ., Aizu-Wakamatsu, Japan
O. Roig, Aizu Univ., Aizu-Wakamatsu, Japan
A. Yakovlev, Aizu Univ., Aizu-Wakamatsu, Japan
pp. 325
F. Corno, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Cusinato, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
M. Ferrero, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
P. Prinetto, Dipartimento di Autom. e Inf., Politecnico di Torino, Italy
pp. 333
Session 7B: Handling Physical Constraints in Architectural Synthesis
Handling Physical Constraints in Architectural Synthesis
N.D. Holmes, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 340
P.K. Jha, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N.D. Dutt, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 345
A. Balboni, Res. & Dev. Lab., Italtel Telecom Co, Italy
C. Costi, Res. & Dev. Lab., Italtel Telecom Co, Italy
A. Pellencin, Res. & Dev. Lab., Italtel Telecom Co, Italy
M. Quadrini, Res. & Dev. Lab., Italtel Telecom Co, Italy
D. Sciuto, Res. & Dev. Lab., Italtel Telecom Co, Italy
pp. 351
Session 7C: Self-Checking Approaches
Self-Checking Approaches
O. Kebichi, Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
Y. Zorian, Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
M. Nicolaidis, Reliable Integrated Syst. Group, TIMA/INPG, Grenoble, France
pp. 358
J.M. Tahir, Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
S.S. Dlay, Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
R.N.G. Naguib, Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
O.R. Hinton, Dept. of Electr. & Electron. Eng., Newcastle upon Tyne Univ., UK
pp. 363
Jing-Jou Tang, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Kuen-Jong Lee, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Bin-Da Liu, Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
pp. 372
Session 8A: Design Methodologies
Design Methodologies
E.K. Vida-Torku, IBM Corp., Austin, TX, USA
C.H. Malley, IBM Corp., Austin, TX, USA
Sung Park, IBM Corp., Austin, TX, USA
R. Reed, IBM Corp., Austin, TX, USA
pp. 378
M. Valle, Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
G. Nateri, Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
D.D. Caviglia, Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
G.M. Bisio, Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
L. Briozzo, Dept. of Biophys. & Electron. Eng., Genoa Univ., Italy
pp. 385
D.L. Andrews, Dept. of Electr. Eng., Arkansas Univ., USA
A. Wheeler, Dept. of Electr. Eng., Arkansas Univ., USA
B. Wealand, Dept. of Electr. Eng., Arkansas Univ., USA
C. Kancler, Dept. of Electr. Eng., Arkansas Univ., USA
pp. 391
Session 8B: Power and Delay Issues in Logic Synthesis
Power and Delay Issues in Logic Synthesis
J. Leijten, Philips Res. Lab., Eindhoven, Netherlands
J. van Meerbergen, Philips Res. Lab., Eindhoven, Netherlands
J. Jess, Philips Res. Lab., Eindhoven, Netherlands
pp. 398
R. Murgai, Fujitsu Labs. of America Inc., San Jose, CA, USA
R.K. Brayton, Fujitsu Labs. of America Inc., San Jose, CA, USA
A. Sangiovanni-Vincentelli, Fujitsu Labs. of America Inc., San Jose, CA, USA
pp. 404
H.H.-F. Jyu, EPIC Desing Technol. Inc., Santa Clara, CA, USA
S. Malik, EPIC Desing Technol. Inc., Santa Clara, CA, USA
pp. 411
Session 8C: BIST Methodologies
BIST Methodologies
B. Wurth, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
K. Fuchs, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 418
C. Dufaza, Lab. d'Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
H. Viallon, Lab. d'Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
C. Chevalier, Lab. d'Inf., de Robotique et de Micro-Electron., CNRS, Montpellier, France
pp. 424
I. Voyiatzis, Inst. of Inf. & Telecommun., NCSR Demokritos, Athens, Greece
A. Paschalis, Inst. of Inf. & Telecommun., NCSR Demokritos, Athens, Greece
D. Nikolos, Inst. of Inf. & Telecommun., NCSR Demokritos, Athens, Greece
C. Halatsis, Inst. of Inf. & Telecommun., NCSR Demokritos, Athens, Greece
pp. 431
Session 9A: New Developments in Logic Representation and Verification Techniques
New Developments in Logic Representation and Verification Techniques
B. Becker, Dept. of Comput. Sci., Frankfurt Univ., Germany
R. Drechsler, Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 438
R. Mukherjee, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
J. Jain, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
M. Fujita, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 444
Session 9C: Test Preparation for Mixed-Signal Systems
Test Preparation for Mixed-Signal Systems
B. Ayari, Ecole Polytech. de Montreal, Que., Canada
N. Ben Hamida, Ecole Polytech. de Montreal, Que., Canada
B. Kaminska, Ecole Polytech. de Montreal, Que., Canada
pp. 458
C. Sebeke, Lab. fur Informationstechnol., Hannover Univ., Germany
J.P. Teixeira, Lab. fur Informationstechnol., Hannover Univ., Germany
M.J. Ohletz, Lab. fur Informationstechnol., Hannover Univ., Germany
pp. 464
Session 10A: Hierarchical Layout
Hierarchical Layout
B. Schurmann, Kaiserslautern Univ., Germany
J. Altmeyer, Kaiserslautern Univ., Germany
pp. 480
H. Schmidt, Cadlab/ASE, Paderborn Univ./Siemens Nixdorf Informationssyst. AG Joint R&D Inst., Germany
D. Theune, Cadlab/ASE, Paderborn Univ./Siemens Nixdorf Informationssyst. AG Joint R&D Inst., Germany
R. Thiele, Cadlab/ASE, Paderborn Univ./Siemens Nixdorf Informationssyst. AG Joint R&D Inst., Germany
T. Lengauer, Cadlab/ASE, Paderborn Univ./Siemens Nixdorf Informationssyst. AG Joint R&D Inst., Germany
pp. 486
M. Hayashi, Fac. of Sci. & Eng., Chuo Univ., Tokyo, Japan
S. Tsukiyama, Fac. of Sci. & Eng., Chuo Univ., Tokyo, Japan
pp. 492
Session 10B: Modeling and Design of ASIPs
Modeling and Design of ASIPs
Jie Gong, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
D.D. Gajski, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
S. Narayan, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 498
A. Fauth, Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
J. Van Praet, Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
M. Freericks, Inst. fur Tech. Inf., Tech. Univ. Berlin, Germany
pp. 503
F. Onion, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
A. Nicolau, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
N. Dutt, Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
pp. 508
Session 10C: Delay Testing and Diagnosis
Delay Testing and Diagnosis
B. Kapoor, Integrated Syst. Labs., Texas Instrum. Inc., Dallas, TX, USA
pp. 516
M. Henftling, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
H. Wittman, Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany
pp. 521
P. Girard, Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
C. Landrault, Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
S. Pravossoudovitch, Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
B. Rodriguez, Lab. d'Inf. de Robotique et de Microelectron. de Montpellier, Univ. des Sci. et Tech. du Languedoc, Montpellier, France
pp. 526
Session 11A: New Applications of Analogue Simulation Algorithms
New Applications of Analogue Simulation Algorithms
L.M. Silveira, Res. Lab. of Electron., MIT, Cambridge, MA, USA
M. Kamon, Res. Lab. of Electron., MIT, Cambridge, MA, USA
J. White, Res. Lab. of Electron., MIT, Cambridge, MA, USA
pp. 534
E. Driouk, Dept. of Microelectron., Byelorussian State Univ. of Inf. & Radioelectron., Minsk, Byelorussia
O. Jarov, Dept. of Microelectron., Byelorussian State Univ. of Inf. & Radioelectron., Minsk, Byelorussia
A. Sukhodolsky, Dept. of Microelectron., Byelorussian State Univ. of Inf. & Radioelectron., Minsk, Byelorussia
pp. 539
Session 11B: Design Problems in Pipelines
Design Problems in Pipelines
M. Rahmouni, Lab. TIMA, Inst. Nat. Polytech. de Grenoble, France
A.A. Jerraya, Lab. TIMA, Inst. Nat. Polytech. de Grenoble, France
pp. 557
Session 11C: IDDQ Testing
IDDQ Testing
M. Dalpasso, Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
M. Favalli, Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
P. Olivo, Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 568
H.-J. Wunderlich, Inst. of Comput. Structures, Siegen Univ., Germany
M. Herzog, Inst. of Comput. Structures, Siegen Univ., Germany
J. Figueras, Inst. of Comput. Structures, Siegen Univ., Germany
J.A. Carrasco, Inst. of Comput. Structures, Siegen Univ., Germany
A. Calderon, Inst. of Comput. Structures, Siegen Univ., Germany
pp. 573
A. Rubio, Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
E. Janssens, Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
H. Casier, Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Figueras, Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
D. Mateo, Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
P. De Pauw, Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
J. Segura, Dept. of Electron. Eng., Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 581
Poster Session
I. Montandon, LSI Logic Corp., CA, USA
D. Burrows, LSI Logic Corp., CA, USA
K. Hunt, LSI Logic Corp., CA, USA
pp. 588
J. Crespo, Telefonica Investigacion y Desarrollo, Madrid, Spain
F. Calvo, Telefonica Investigacion y Desarrollo, Madrid, Spain
J.I. Solana, Telefonica Investigacion y Desarrollo, Madrid, Spain
R. Caravantes, Telefonica Investigacion y Desarrollo, Madrid, Spain
J.L. Conesa, Telefonica Investigacion y Desarrollo, Madrid, Spain
pp. 589
G.-P.K. Economou, VLSI Design Lab., Patras Univ., Greece
J.A. Hallas, VLSI Design Lab., Patras Univ., Greece
E.P. Mariatos, VLSI Design Lab., Patras Univ., Greece
C.E. Goutis, VLSI Design Lab., Patras Univ., Greece
pp. 590
D.A. Bensouiah, Centre for VLSI Design, Essex Univ., Colchester, UK
R.J. Mack, Centre for VLSI Design, Essex Univ., Colchester, UK
R.E. Massara, Centre for VLSI Design, Essex Univ., Colchester, UK
pp. 591
B. Becker, Dept. of Comput. Sci., Frankfurt Univ., Germany
R. Drechsler, Dept. of Comput. Sci., Frankfurt Univ., Germany
pp. 592
R. Rochet, Inst. Nat. Polytech. de Grenoble, France
R. Leveugle, Inst. Nat. Polytech. de Grenoble, France
G. Saucier, Inst. Nat. Polytech. de Grenoble, France
pp. 593
H. Selvaraj, Inst. of Telecommun., Warsaw Univ. of Technol., Poland
T. Luba, Inst. of Telecommun., Warsaw Univ. of Technol., Poland
pp. 594
H. Fujisawa, Fujitsu Labs. Ltd., Atsugi, Japan
F. Kawafuji, Fujitsu Labs. Ltd., Atsugi, Japan
T. Kitaura, Fujitsu Labs. Ltd., Atsugi, Japan
T. Kage, Fujitsu Labs. Ltd., Atsugi, Japan
pp. 595
A.J. Van Genderen, Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
pp. 596
W. Pleskacz, Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland
W. Kuzmicz, Inst. of Microelectron. & Optoelectron., Warsaw Univ. of Technol., Poland
pp. 598
M. Favalli, Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
B. Ricco, Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
L. Penza, Dipartimento di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
pp. 599
J. Carletta, Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
C. Papachristou, Dept. of Comput. Eng. & Sci., Case Western Reserve Univ., Cleveland, OH, USA
pp. 600
V. Szekely, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
M. Rencz, Dept. of Electron Devices, Tech. Univ. Budapest, Hungary
pp. 601
A. Romankevich, Kiev Polytech. Inst., Ukraine
V. Groll, Kiev Polytech. Inst., Ukraine
pp. 602
R.Kh. Latypov, Kazan State Univ., Russia
Y.L. Stolov, Kazan State Univ., Russia
pp. 603
M.B. Santos, INESC, Lisbon, Portugal
M. Simoes, INESC, Lisbon, Portugal
I. Teixeira, INESC, Lisbon, Portugal
J.P. Teixeira, INESC, Lisbon, Portugal
pp. 604
D. Dallet, Lab. de Microelectron., Bordeaux I Univ., Talence, France
G. Franco, Lab. de Microelectron., Bordeaux I Univ., Talence, France
P. Marchegay, Lab. de Microelectron., Bordeaux I Univ., Talence, France
C. Morandi, Lab. de Microelectron., Bordeaux I Univ., Talence, France
pp. 606
V. Zagursky, Inst. of Electron. & Comput. Sci., Acad. of Sci., Riga, Latvia
N. Semyonova, Inst. of Electron. & Comput. Sci., Acad. of Sci., Riga, Latvia
M. Sirovatkina, Inst. of Electron. & Comput. Sci., Acad. of Sci., Riga, Latvia
pp. 607
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