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15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems (ecbs 2008)
Interrupt Costs in Embedded System with Short Latency Hardware Accelerators
March 31-April 04
ISBN: 978-0-7695-3141-0
| ASCII Text | x | ||
| S?bastien Lafond, Johan Lilius, "Interrupt Costs in Embedded System with Short Latency Hardware Accelerators," Engineering of Computer-Based Systems, IEEE International Conference on the, pp. 317-325, 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems (ecbs 2008), 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/ECBS.2008.39, author = {S?bastien Lafond and Johan Lilius}, title = {Interrupt Costs in Embedded System with Short Latency Hardware Accelerators}, journal ={Engineering of Computer-Based Systems, IEEE International Conference on the}, volume = {0}, year = {2008}, isbn = {978-0-7695-3141-0}, pages = {317-325}, doi = {http://doi.ieeecomputersociety.org/10.1109/ECBS.2008.39}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - Engineering of Computer-Based Systems, IEEE International Conference on the TI - Interrupt Costs in Embedded System with Short Latency Hardware Accelerators SN - 978-0-7695-3141-0 SP317 EP325 A1 - S?bastien Lafond, A1 - Johan Lilius, PY - 2008 KW - Hardware accelerator KW - Interrupt VL - 0 JA - Engineering of Computer-Based Systems, IEEE International Conference on the ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/ECBS.2008.39
The current trend for handheld device is to provide the users various embedded multimedia applications. These new applications constrain architecture developers to embed dedicated hardware accelerators in order to meet the application timing requirements. However the use of dedicated monolithic hardware accelerators is onerous to achieve due to physical and economical constraints. When the multimedia applications share common functionalities, monolithic hardware accelerators could be split into smaller accelerators in order to cut down redundancy in hardware implemented functionalities and save silicon area. Nevertheless lowering the granularity of accelerator will increase synchronization calls between the main processor and the accelerators. This paper presents a methodology for analyzing the impact of short latency hardware accelerators on a typical embedded system. We show that hardware accelerator granularity has a direct effect on the system performance in terms of cache misses, execution time and thus energy consumption.
Index Terms:
Hardware accelerator, Interrupt
Citation:
S?bastien Lafond, Johan Lilius, "Interrupt Costs in Embedded System with Short Latency Hardware Accelerators," ecbs, pp.317-325, 15th Annual IEEE International Conference and Workshop on the Engineering of Computer Based Systems (ecbs 2008), 2008
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