[Front cover]

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

[Copyright notice] (PDF)

pp. iv

Table of contents (PDF)

pp. v-xv

Message from the Program Chair (PDF)

pp. xvi-xvii

Conference Committees (PDF)

pp. xviii-xxiii

Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care (Abstract) (Abstract)

Harmke de Groot

pp. 3

PDF

Human++: Key Challenges and Trade-offs in Embedded System Design for Personal Health Care (Abstract)

pp. 4-10

PDF

Cryptographic Contests: Toward Fair and Comprehensive Benchmarking of Cryptographic Algorithms in Hardware (Abstract) (Abstract)

Kris Gaj

pp. 11

PDF

The Future of Data-Parallel Embedded Systems (Abstract) (Abstract)

Menno M. Lindwer

pp. 12

PDF

Generalized If-Then-Else Operator for Compact Polynomial Representation of Multi Output Functions (Abstract)

Ilya Levin

Osnat Keren

pp. 15-20

PDF

On the Cascade Implementation of Multiple-Output Sparse Logic Functions (Abstract)

V´clav Dvor´k

Petr Mikušek

pp. 21-28

PDF

Mohammad Hossein Neishaburi

On Failure Rate Assessment Using an Executable Model of the System (Abstract)

Zeljko Zilic

pp. 29-36

PDF

A Cost Effective Centralized Adaptive Routing for Networks-on-Chip (Abstract)

pp. 39-46

PDF

Realization and Scalability of Release and Protected Release Consistency Models in NoC Based Systems (Abstract)

pp. 47-54

PDF

Numeral-Based Crosstalk Avoidance Coding to Reliable NoC Design (Abstract)

Mansour Shafaei

Ahmad Patooghy

Seyed Ghassem Miremadi

pp. 55-62

PDF

A Fast Congestion-Aware Flow Control Mechanism for ID-Based Networks-on-Chip with Best-Effort Communication (Abstract)

pp. 63-70

PDF

Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture (Abstract)

Fahimeh Jafari

Shuo Li

Ahmed Hemani

pp. 73-80

PDF

VMAP: A Variation Map-Aware Placement Algorithm for Leakage Power Reduction in FPGAs (Abstract)

pp. 81-87

PDF

PUMA: Placement Unification with Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoC (Abstract)

Muhammad Aqeel Wahlah

Kees Goossens

pp. 88-96

PDF

Improved Power Modeling of DDR SDRAMs (Abstract)

pp. 99-108

PDF

Path-Based Dynamic Voltage and Frequency Scaling Algorithms for Multiprocessor Embedded Applications with Soft Delay Deadlines (Abstract)

pp. 109-116

PDF

Power Minimisation for Real-Time Dataflow Applications (Abstract)

pp. 117-124

PDF

VHDL Code Generation from Formal Event-B Models (Abstract)

Sergey Ostroumov

Leonidas Tsiopoulos

pp. 127-134

PDF

Process Variation Reduction for CMOS Logic Operating at Sub-threshold Supply Voltage (Abstract)

Bo Liu

Hamid Reza Pourshaghaghi

Sebastian Moreno Londoño

José Pineda de Gyvez

pp. 135-139

PDF

Hardware Reuse in Modern Application-Specific Processors and Accelerators (Abstract)

pp. 140-147

PDF

Quaternary High Performance Arithmetic Logic Unit Design (Abstract)

A.N. Nagamani

S. Nishchai

pp. 148-153

PDF

Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers (Abstract)

Jean Michel Chabloz

Ahmed Hemani

pp. 157-164

PDF

Towards an Efficient NoC Topology through Multiple Injection Ports (Abstract)

pp. 165-172

PDF

LastZ: An Ultra Optimized 3D Networks-on-Chip Architecture (Abstract)

Amir-Mohammad Rahmani

pp. 173-180

PDF

Comparison of Different Thread Scheduling Strategies for Asymmetric Chip MultiThreading Architectures in Embedded Systems (Abstract)

pp. 181-187

PDF

SAT-Based Generation of Compressed Skewed-Load Tests for Transition Delay Faults (Abstract)

Roland Dobai

Marcel Bal´ž

pp. 191-196

PDF

Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation (Abstract)

pp. 197-204

PDF

Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles (Abstract)

Richard Ruzicka

Vaclav Simek

pp. 205-212

PDF

A Technique for Accelerating Injection of Transient Faults in Complex SoCs (Abstract)

Alireza Rohani

Hans G. Kerkhoff

pp. 213-220

PDF

SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems (Abstract)

pp. 223-230

PDF

Fault Tolerance of Multiple Logic Faults in SRAM-Based FPGA Systems (Abstract)

pp. 231-238

PDF

Reliability-Aware Design Optimization for Multiprocessor Embedded Systems (Abstract)

pp. 239-246

PDF

Design of Asynchronous Circuits on FPGAs for Soft Error Tolerance (Abstract)

Yu Bai

Weidong Kuang

pp. 247-253

PDF

HMMER Performance Model for Multicore Architectures (Abstract)

pp. 257-261

PDF

Kactus2: Environment for Embedded Product Development Using IP-XACT and MCAPI (Abstract)

pp. 262-265

PDF

10-Gigabit Throughput and Low Area for a Hardware Implementation of the Advanced Encryption Standard (Abstract)

Paolo Maistri

Régis Leveugle

pp. 266-269

PDF

Multicore Cache Simulations Using Heterogeneous Computing on General Purpose and Graphics Processors (Abstract)

pp. 270-273

PDF

Power Spectral Density Side Channel Attack Overlapping Window Method (Abstract)

pp. 274-278

PDF

Dynamic Power Estimation for Motion Estimation Hardware (Abstract)

Caglar Kalaycioglu

Ilker Hamzaoglu

pp. 279-282

PDF

A Module for Packet Hijacking in NetFPGA Platform (Abstract)

pp. 283-286

PDF

Fault Models Usability Study for On-line Tested FPGA (Abstract)

pp. 287-290

PDF

Hardware Implementation of a Flexible Tag Platform for Passive RFID Devices (Abstract)

Thomas Plos

Martin Feldhofer

pp. 293-300

PDF

Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder (Abstract)

pp. 301-308

PDF

An Overlapped Block Motion Compensation Hardware for Frame Rate Conversion (Abstract)

pp. 309-315

PDF

Cost of Sparse Mesh Layouts Supporting Throughput Computing (Abstract)

pp. 316-323

PDF

An Environment for (re)configuration and Execution Managenment of Flexible Radio Platforms (Abstract)

pp. 327-334

PDF

FBMC and GFDM Interference Cancellation Schemes for Flexible Digital Radio PHY Design (Abstract)

pp. 335-339

PDF

A Novel Architecture for Scalable, High Throughput, Multi-standard LDPC Decoder (Abstract)

pp. 340-347

PDF

A Non-Intrusive Online FPGA Test Scheme Using a Hardwired Network on Chip (Abstract)

Muhammad Aqeel Wahlah

Kees Goossens

pp. 351-359

PDF

Techniques for SAT-Based Constrained Test Pattern Generation (Abstract)

pp. 360-366

PDF

On RTL Testability and Gate-Level Stuck-At-Fault Coverage Correlation for Scan Circuits (Abstract)

Michal Rumplík

Josef Strnadel

pp. 367-374

PDF

An Enhanced Path Delay Fault Simulator for Combinational Circuits (Abstract)

pp. 375-381

PDF

Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling (Abstract)

pp. 385-392

PDF

Design of Fault Tolerant Network Interfaces for NoCs (Abstract)

pp. 393-400

PDF

Designing Robust Asynchronous Circuits Based on FinFET Technology (Abstract)

pp. 401-408

PDF

Analyzing Area Penalty of 32-Bit Fault Tolerant ALU Using BCH Code (Abstract)

Vahid Khorasani

Bijan Vosoughi Vahdat

Mohammad Mortazavi

pp. 409-413

PDF

Low Power FPGA Implementations of JH and Fugue Hash Functions (Abstract)

pp. 417-421

PDF

Mutant Fault Injection in Functional Properties of a Model to Improve Coverage Metrics (Abstract)

Ali Abbasinasab

Mehdi Mohammadi

Siamak Mohammadi

Svetlana Yanushkevich

Michael Smith

pp. 422-425

PDF

A Unified Architecture for BCD and Binary Adder/Subtractor (Abstract)

V. Chetan Kumar

P. Sai Phaneendra

Syed Ershad Ahmed

Sreehari Veeramachaneni

N. Moorthy Muthukrishnan

M.B. Srinivas

pp. 426-429

PDF

Synthesizing Concurrent Synchronous Computing Machines from Interrupt-Driven Binaries (Abstract)

Michael D. Wilder

Robert E. Rinker

pp. 430-433

PDF

Architectures for Fast Modular Multiplication (Abstract)

pp. 434-437

PDF

Transaction Level Modeling of a Networked Embedded System Based on a Power Line Communication Protocol (Abstract)

pp. 438-441

PDF

Nexus: Hardware Support for Task-Based Programming (Abstract)

Cor Meenderinck

Ben Juurlink

pp. 442-445

PDF

Evaluation of Fault-Tolerant Routing Methods for NoC Architectures (Abstract)

Mojtaba Valinataj

pp. 446-449

PDF

On the Design of Modulo 2^n+1 Multipliers (Abstract)

Constantinos Efstathiou

Kiamal Pekmestzi

Nicholas Axelos

pp. 453-459

PDF

Binary-to-RNS Conversion Units for moduli {2^n ± 3} (Abstract)

Pedro Miguens Matutino

Ricardo Chaves

Leonel Sousa

pp. 460-467

PDF

Modulo 2^n+1 Arithmetic Units with Embedded Diminished-to-Normal Conversion (Abstract)

pp. 468-475

PDF

Automated Design Debugging in a Testbench-Based Verification Environment (Abstract)

pp. 479-486

PDF

Efficient Fault Simulation of SystemC Designs (Abstract)

Weiyun Lu

Martin Radetzki

pp. 487-494

PDF

Higher-Order Abstraction in Hardware Descriptions with C?aSH (Abstract)

pp. 495-502

PDF

Thermal Effect of TSVs in 3D Die-Stacked Integrated Circuits (Abstract)

Hadrien A. Clarke

Kazuaki Murakami

pp. 503-508

PDF

A Parallel Ray Tracing Architecture Suitable for Application-Specific Hardware and GPGPU Implementations (Abstract)

pp. 511-518

PDF

Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots (Abstract)

pp. 519-524

PDF

Microthreading as a Novel Method for Close Coupling of Custom Hardware Accelerators to SVP Processors (Abstract)

pp. 525-532

PDF

Pre-silicon Characterization of NIST SHA-3 Final Round Candidates (Abstract)

Xu Guo

pp. 535-542

PDF

Novel Hardware Architecture for Implementing the Inner Loop of the SHA-2 Algorithms (Abstract)

Ignacio Algredo-Badillo

Claudia Feregrino-Uribe

René Cumplido

Miguel Morales-Sandoval

pp. 543-549

PDF

Modular Fault Injector for Multiple Fault Dependability and Security Evaluations (Abstract)

pp. 550-557

PDF

Breaking Hitag2 with Reconfigurable Hardware (Abstract)

Petr Štembera

Martin Novotný

pp. 558-563

PDF

Iteration-Based Trade-Off Analysis of Resource-Aware SDF (Abstract)

pp. 567-574

PDF

SoC and Board Modeling for Processor-Centric Board Testing (Abstract)

pp. 575-582

PDF

Hybrid Code-Data Prefetch-Aware Multiprocessor Task Graph Scheduling (Abstract)

Morteza Damavandpeyma

pp. 583-590

PDF

Efficient CRT RSA with SCA Countermeasures (Abstract)

Apostolos P. Fournaris

Odysseas Koufopavlou

pp. 593-599

PDF

Daniel Mueller-Gritschneder

Control-Flow-Driven Source Level Timing Annotation for Embedded Software Models on Transaction Level (Abstract)

Kun Lu

Ulf Schlichtmann

pp. 600-607

PDF

HDL-Mutation Based Simulation Data Generation by Propagation Guided Search (Abstract)

Tao Xie

Wolfgang Mueller

Florian Letombe

pp. 608-615

PDF

Miguel Ángel S´nchez Marcos

On-chip Monitoring: A Light-Weight Interconnection Network Approach (Abstract)

Pablo Ituero

Marisa López-Vallejo

Carlos Gómez Osuna

pp. 619-625

PDF

Enhancing Performance Sustainability of Fault Tolerant Routing Algorithms in NoC-Based Architectures (Abstract)

Khalid Latif

Amir-Mohammad Rahmani

pp. 626-633

PDF

Formal Modeling of Multicast Communication in 3D NoCs (Abstract)

pp. 634-642

PDF

Thermal Analysis of Job Allocation and Scheduling Schemes for 3D Stacked NoC's (Abstract)

Kameswar Rao Vaddina

Amir-Mohammad Rahmani

pp. 643-648

PDF

A Configurable Ring-Oscillator-Based PUF for Xilinx FPGAs (Abstract)

Xin Xin

Jens-Peter Kaps

Kris Gaj

pp. 651-657

PDF

A Unified Multiply/Accumulate Unit for Pairing-Based Cryptography over Prime, Binary and Ternary Fields (Abstract)

pp. 658-666

PDF

A Novel Architecture of Implementing Error Detecting AES Using PRNS (Abstract)

Junfeng Chu

Mohammed Benaissa

pp. 667-673

PDF

How a Symmetry Metric Assists Side-Channel Evaluation - A Novel Model Verification Method for Power Analysis (Abstract)

pp. 674-681

PDF

Rapid and Accurate Leakage Power Estimation for Nano-CMOS Circuits (Abstract)

pp. 685-692

PDF

An Energy Aware Design Space Exploration for VLIW AGU Model with Fine Grained Power Gating (Abstract)

pp. 693-700

PDF

A Design Method for Programmable Two-Variable Discrete Function Generators Using Spline and Bilinear Interpolations (Abstract)

Satoru Nakano

Yoichi Wakaba

Shinobu Nagayama

Shin'ichi Wakabayashi

pp. 701-707

PDF

Exploiting Inter and Intra Application Dynamism to Save Energy (Abstract)

pp. 708-715

PDF

Model Driven Cache-Aware Scheduling of Object Oriented Software for Chip Multiprocessors (Abstract)

Tolga Ovatman

Feza Buzluca

pp. 719-726

PDF

Compiling Esterel for Multi-core Execution (Abstract)

pp. 727-735

PDF

Phase-Guided Scheduling on Single-ISA Heterogeneous Multicore Processors (Abstract)

pp. 736-745

PDF

Energy Behaviour of NUCA Caches in CMPs (Abstract)

pp. 746-753

PDF

A Wearable Intelligent System for the Health of Expectant Mom's and of Their Children (Abstract)

pp. 757-763

PDF

Embedded System for Camera-Based TV Power Reduction (Abstract)

pp. 764-768

PDF

An Embedded Video Sensor for a Smart Traffic Light (Abstract)

Guido Matrella

Davide Marani

pp. 769-776

PDF

On the Efficiency of Design Time Evaluation of the Resistance to Power Attacks (Abstract)

pp. 777-785

PDF

Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring (Abstract)

pp. 789-792

PDF

Automatic Interface Generation for Component Reuse in HW-SW Partitioning (Abstract)

pp. 793-796

PDF

A Scalable Distributed Asynchronous Control Network for High Level Synthesis of Digital Circuits (Abstract)

Tom van Leeuwen

Rene van Leuken

pp. 797-800

PDF

A Process-Variation-Adaptive Network-on-Chip with Variable-Cycle Routers (Abstract)

pp. 801-804

PDF

Faster Processor Allocation Algorithms for Mesh-Connected CMPs (Abstract)

pp. 805-808

PDF

Compatibility Study of Compile-Time Optimizations for Power and Reliability (Abstract)

pp. 809-813

PDF

An FPGA Implementation of the ZUC Stream Cipher (Abstract)

Paris Kitsos

Nicolas Sklavos

Athanassios N. Skodras

pp. 814-817

PDF

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC (Abstract)

Ashkan Beyranvand Nejad

Anca Molnos

Kees Goossens

pp. 818-822

PDF

Author Index (PDF)

pp. 823-827

[Publishers information] (PDF)

pp. 828