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2011 14th Euromicro Conference on Digital System Design
Efficient Fault Simulation of SystemC Designs
Oulu, Finland
August 31-September 02
ISBN: 978-0-7695-4494-6
| ASCII Text | x | ||
| Weiyun Lu, Martin Radetzki, "Efficient Fault Simulation of SystemC Designs," 2012 15th Euromicro Conference on Digital System Design, pp. 487-494, 2011 14th Euromicro Conference on Digital System Design, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/DSD.2011.68, author = {Weiyun Lu and Martin Radetzki}, title = {Efficient Fault Simulation of SystemC Designs}, journal ={2012 15th Euromicro Conference on Digital System Design}, volume = {0}, year = {2011}, isbn = {978-0-7695-4494-6}, pages = {487-494}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2011.68}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 15th Euromicro Conference on Digital System Design TI - Efficient Fault Simulation of SystemC Designs SN - 978-0-7695-4494-6 SP487 EP494 A1 - Weiyun Lu, A1 - Martin Radetzki, PY - 2011 KW - SystemC KW - fault simulation KW - concurrent and comparative simulation KW - robustness VL - 0 JA - 2012 15th Euromicro Conference on Digital System Design ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2011.68
In this paper we present extensions to the SystemC library and automatable model transformations that enable efficient system-level fault simulation in SystemC. The method is based on extended data types which represent variables or signals as lists of values (instead of one value) consisting of a fault free reference value and any number of faulty values each of which corresponds to one fault. Faults (variable level faults as well as bit level faults) are injected to objects declared with the extended data types and are then propagated to other variables or SystemC channels during SystemC simulation, until either they are classified and dropped or the simulation ends. This work enables concurrent simulation of many faults in one SystemC simulation run. Two case studies exhibit a speedup up to 9 and 665 for permanent and transient variable level faults.
Index Terms:
SystemC, fault simulation, concurrent and comparative simulation, robustness
Citation:
Weiyun Lu, Martin Radetzki, "Efficient Fault Simulation of SystemC Designs," dsd, pp.487-494, 2011 14th Euromicro Conference on Digital System Design, 2011
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