CSDL - Proceedings D

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-xiv

Conference Information (PDF)

pp. xv-xxix

A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC (Abstract)

pp. 3-10

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An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs (Abstract)

pp. 11-18

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An Effective Replacement Strategy of Cache Memory for an SMT Processor (Abstract)

Yoshiyasu Ogasawara

Hironori Nakajo

pp. 19-25

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An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload (Abstract)

pp. 26-33

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A Priority-Based Budget Scheduler with Conservative Dataflow Model (Abstract)

pp. 37-44

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Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation (Abstract)

Alexandru Amaricai

Oana Boncalo

pp. 45-49

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Distributed Collaborative Design of a Mixed-Signal IP Component (Abstract)

pp. 50-57

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A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling (Abstract)

Mohammad Fattah

Soodeh Aghli Moghaddam

Siamak Mohammadi

pp. 61-66

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Improving Latency of Quantum Circuits by Gate Exchanging (Abstract)

pp. 67-73

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Run-Time Reconfigurable Array Using Magnetic RAM (Abstract)

pp. 74-81

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Robustness Check for Multiple Faults Using Formal Techniques (Abstract)

pp. 85-90

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Instruction Precomputation for Fault Detection (Abstract)

Demid Borodin

B.H.H. (Ben) Juurlink

Stefanos Kaxiras

pp. 91-99

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Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic (Abstract)

Werner Friesenbichler

Andreas Steininger

pp. 100-107

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High Availability Fault Tolerant Architectures Implemented into FPGAs (Abstract)

Martin Straka

Zdenek Kotasek

pp. 108-115

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Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip (Abstract)

pp. 119-126

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Exploration of Slot Allocation for On-Chip TDM Virtual Circuits (Abstract)

Li Tong

Zhonghai Lu

Hua Zhang

pp. 127-132

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Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms (Abstract)

Amit Kumar Singh

Wu Jigang

Alok Prakash

Thambipillai Srikanthan

pp. 133-140

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Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks (Abstract)

pp. 141-146

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Power Management Aware Low Leakage Behavioural Synthesis (Abstract)

pp. 149-156

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Variation-tolerant Design Using Residue Number System (Abstract)

Ioannis Kouretas

Vassilis Paliouras

pp. 157-163

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Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis (Abstract)

George Economakos

Sotiris Xydis

pp. 164-171

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Combined SD-RNS Constant Multiplication (Abstract)

E. Vassalos

D. Bakalis

pp. 172-179

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Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures (Abstract)

Ayse K. Coskun

Andrew B. Kahng

Tajana Simunic Rosing

pp. 183-190

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Calibration Method for a CMOS 0.06mm^2 150MS/s 8-bit ADC (Abstract)

pp. 191-195

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Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications (Abstract)

José Carlos García-Montesdeoca

Juan A. Montiel-Nelson

Saeid Nooshabadi

J. Sosa

Héctor Navarro

pp. 196-199

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An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs (Abstract)

pp. 203-206

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Model-Driven Design of Embedded Multimedia Applications on SoCs (Abstract)

pp. 207-210

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Felipe Maia Galvão França

GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids (Abstract)

Alexandre Solon Nery

Nadia Nedjah

pp. 211-216

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Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors (Abstract)

pp. 217-220

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Heinrich Theodor Vierhaus

Reliability Estimation Process (Abstract)

T. Koal

Daniel Scheit

pp. 221-224

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Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems (Abstract)

pp. 225-228

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Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems (Abstract)

pp. 229-232

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High Performance Image Processing on a Massively Parallel Processor Array (Abstract)

pp. 233-236

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Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment (Abstract)

pp. 239-246

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Low Power Encoding in NoCs Based on Coupling Transition Avoidance (Abstract)

Meysam Taassori

Shaahin Hessabi

pp. 247-254

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Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources (Abstract)

pp. 255-262

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Storage Architecture for an On-chip Multi-core Processor (Abstract)

Mengxiao Liu

Weixing Ji

Jiaxin Li

Xing Pu

pp. 263-270

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Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs (Abstract)

pp. 273-280

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Fariborz Fereydouni Forouzandeh

A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC (Abstract)

Feng Liu

pp. 281-286

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Streaming Reduction Circuit (Abstract)

pp. 287-292

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Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation (Abstract)

Daniel Piso Fernandez

Javier Diaz Bruguera

pp. 293-300

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Pulse Generation for On-chip Data Transmission (Abstract)

Simon J. Hollis

pp. 303-310

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José Carlos García-Montesdeoca

High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output (Abstract)

Juan A. Montiel-Nelson

Saeid Nooshabadi

pp. 311-314

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Performance-Effective Compaction of Standard-Cell Libraries for Digital Design (Abstract)

pp. 315-322

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On the Risk of Fault Coupling over the Chip Substrate (Abstract)

Peter Tummeltshammer

Andreas Steininger

pp. 325-332

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Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints (Abstract)

Makoto Sugihara

pp. 333-340

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Letícia Maria Bolzani Pöhls

A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems (Abstract)

Jimmy Tarrillo

Fabian Vargas

pp. 341-347

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Reliable Railway Station System Based on Regular Structure Implemented in FPGA (Abstract)

pp. 348-354

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Dependable Controller Design Using Polymorphic Counters (Abstract)

Richard Ruzicka

pp. 355-362

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Internet-Router Buffered Crossbars Based on Networks on Chip (Abstract)

pp. 365-374

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Network-on-Chip Architecture Exploration Framework (Abstract)

pp. 375-382

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Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip (Abstract)

pp. 383-389

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Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study (Abstract)

pp. 390-397

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A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning (Abstract)

Ahmed Mohamed AbdelHamid

Ankur Anchlia

Stylianos Mamagkakis

Miguel Corbalan Miranda

Bart Dierickx

Maarten Kuijk

pp. 401-408

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Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors (Abstract)

Anca Molnos

Kees Goossens

pp. 409-418

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Compilation Technique for Loop Overhead Minimization (Abstract)

pp. 419-426

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Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip (Abstract)

Ming Li

pp. 427-432

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Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques (Abstract)

pp. 435-440

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Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator (Abstract)

Panayiotis Savvopoulos

Nikolaos Papandreou

Theodore Antonakopoulos

pp. 441-448

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An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application (Abstract)

pp. 449-456

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Deductive Fault Simulation for Asynchronous Sequential Circuits (Abstract)

Roland Dobai

Elena Gramatová

pp. 459-464

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ARROW - A Generic Hardware Fault Injection Tool for NoCs (Abstract)

Michael Birner

Thomas Handl

pp. 465-472

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A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction (Abstract)

pp. 473-480

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Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation (Abstract)

Oana Boncalo

Alexandru Amaricai

pp. 481-487

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High Reliable Remote Terminal Unit for Space Applications (Abstract)

pp. 488-493

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SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform (Abstract)

Asadollah Shahbahrami

Ben Juurlink

pp. 497-504

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Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism (Abstract)

Zheng Shen

Hu He

Yihe Sun

pp. 505-512

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Iterative Algorithm for Compound Instruction Selection with Register Coalescing (Abstract)

pp. 513-520

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CPLD-oriented Synthesis of Finite State Machines (Abstract)

Robert Czerwinski

Dariusz Kania

pp. 521-528

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Architecture-Driven Synthesis of Reconfigurable Cells (Abstract)

pp. 531-538

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An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication (Abstract)

pp. 539-546

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Composable Resource Sharing Based on Latency-Rate Servers (Abstract)

pp. 547-555

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A MPSoC Prototyping Platform for Flexible Radio Applications (Abstract)

pp. 559-566

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Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation (Abstract)

pp. 567-574

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Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems (Abstract)

pp. 575-581

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Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm (Abstract)

pp. 582-589

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José Carlos García-Montesdeoca

High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic (Abstract)

Juan A. Montiel-Nelson

Saeid Nooshabadi

pp. 593-596

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Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks (Abstract)

pp. 597-600

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The Case for a Balanced Decomposition Process (Abstract)

Jan Schmidt

Petr Fišer

pp. 601-604

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Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization (Abstract)

Petr Mikušek

Václav Dvorák

pp. 605-608

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Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder (Abstract)

pp. 609-612

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Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture (Abstract)

pp. 613-616

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Survey of Test Data Compression Technique Emphasizing Code Based Schemes (Abstract)

pp. 617-620

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Heinrich Theodor Vierhaus

A Concept for Logic Self Repair (Abstract)

Tobias Koal

Daniel Scheit

pp. 621-624

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A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor (Abstract)

pp. 627-634

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An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions (Abstract)

pp. 635-642

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Gianmarco De Francisci Morales

An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures (Abstract)

Vincenzo Catania

Alessandro G. Di Nuovo

Maurizio Palesi

Davide Patti

pp. 643-650

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Energy and Performance Model of a SPARC Leon3 Processor (Abstract)

pp. 651-656

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Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers (Abstract)

Lu Gao

Li Guo

Canxing Lu

pp. 659-666

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FPGA Accelerator for RNA Secondary Structure Prediction (Abstract)

Arturo Díaz-Pérez

Mario A. García-Martínez

pp. 667-671

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An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm (Abstract)

pp. 672-679

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xMAML: A Modeling Language for Dynamically Reconfigurable Architectures (Abstract)

pp. 680-687

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A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation (Abstract)

pp. 691-698

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Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution (Abstract)

Di Wu

pp. 699-706

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GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations (Abstract)

pp. 707-713

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A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video (Abstract)

Ozgur Tasdizen

Ilker Hamzaoglu

pp. 714-719

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Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models (Abstract)

Antonio da Silva

Sebastián Sánchez

pp. 723-728

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Design of a Highly Dependable Beamforming Chip (Abstract)

Xiao Zhang

Hans G. Kerkhoff

pp. 729-735

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One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm (Abstract)

Apostolos P. Fournaris

Odysseas Koufopavlou

pp. 736-741

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Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links (Abstract)

pp. 742-745

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Synthesizing Reversible Circuits for Irreversible Functions (Abstract)

pp. 749-756

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A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms (Abstract)

Petr Fišer

David Toman

pp. 757-764

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Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables (Abstract)

pp. 765-772

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Logic Minimization and Testability of 2SPP-P-Circuits (Abstract)

pp. 773-780

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FPGA Implementations of SHA-3 Candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash (Abstract)

pp. 783-790

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Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology (Abstract)

pp. 791-798

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Mario Alberto Ibarra-Manzano

Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization (Abstract)

Dora-Luz Almanza-Ojeda

pp. 799-805

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The Parallel Sieve Method for a Virus Scanning Engine (Abstract)

pp. 809-816

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Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm (Abstract)

Hamid Reza Ahmadi

Ali Afzali-Kusha

pp. 817-822

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Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing (Abstract)

pp. 823-829

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An FPGA-Based Embedded System for a Sailing Robot (Abstract)

José Carlos Alves

Nuno Alexandre Cruz

pp. 830-837

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Ad-hoc WSN in Biological Research (Abstract)

Perfecto Mariño

Fernando Pérez Fontán

Miguel Ángel Domínguez

Santiago Otero

pp. 841-848

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Low Power Free Space Optical Communication in Wireless Sensor Networks (Abstract)

pp. 849-856

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A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes (Abstract)

Carlo Brandolese

William Fornaciari

pp. 857-864

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Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds (Abstract)

pp. 865-869

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Author Index (PDF)

pp. 870-874

Roster Page (PDF)

pp. 876