CSDL - Proceedings D

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-xiv

Message from the Program Chair (PDF)

pp. xv

Message from the General and Organizing Chairs (PDF)

pp. xvi

Conference Committees (PDF)

pp. xvii-xxi

Keynote Abstract: Rich Goldman (PDF)

pp. xxii

Keynote Abstract: Alessandro Cremonesi (PDF)

pp. xxiii

Keynote Abstract: Thomas Williams (PDF)

pp. xxiv

Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform (Abstract)

null Kouadri-Mostefaoui

null Abdellah-Medjadji

Benaoumeur Senouci

Frederic Petrot

pp. 3-9

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Network Interface Sharing Techniques for Area Optimized NoC Architectures (Abstract)

pp. 10-17

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Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links (Abstract)

pp. 18-25

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CART: Communication-Aware Routing Technique for Application-Specific NoCs (Abstract)

pp. 26-31

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LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control (Abstract)

pp. 32-35

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Flexible Baseband Architectures for Future Wireless Systems (Abstract)

Najam-ul-Islam Muhammad

pp. 39-46

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A Lightweight Operating Environment for Next Generation Cognitive Radios (Abstract)

pp. 47-52

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On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip (Abstract)

pp. 53-60

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A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity Analysis (Abstract)

pp. 61-67

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Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems (Abstract)

pp. 71-80

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Digital Systems Architectures Based on On-line Checkers (Abstract)

pp. 81-87

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Fault Models and Injection Strategies in SystemC Specifications (Abstract)

pp. 88-95

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An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA (Abstract)

pp. 96-99

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Experimental SEU Impact on Digital Design Implemented in FPGAs (Abstract)

pp. 100-103

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Temperature and Leakage Aware Power Control for Embedded Streaming Applications (Abstract)

pp. 107-114

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Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software (Abstract)

Carlo Brandolese

pp. 115-123

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Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations (Abstract)

pp. 124-130

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A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips (Abstract)

Markus Winter

Gerhard P. Fettweis

pp. 133-140

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A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching (Abstract)

pp. 141-148

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A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures (Abstract)

pp. 149-157

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A Modular Approach to Model Heterogeneous MPSoC at Cycle Level (Abstract)

pp. 158-164

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Performance and Timing Yield Enhancement using Highway-on-Chip Planning (Abstract)

Ali Jahanian

Morteza Saheb Zamani

pp. 165-172

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An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures (Abstract)

Thomas S?dring

?shild Gr?nstad Solheim

Tor Skeie

Sven-Arne Reinemo

pp. 173-178

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Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units (Abstract)

pp. 181-188

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Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture (Abstract)

pp. 189-194

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Design of a Two Dimensional PRSI Image Processor (Abstract)

Theja Tulabandhula

Amit Patra

Nirmal B. Chakrabarti

pp. 195-202

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A Hardware Design for Camera-Based Power Management of Computer Monitor (Abstract)

pp. 203-209

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Co-design and Implementation of the H.264/AVC Motion Estimation Algorithm Using Co-simulation (Abstract)

pp. 210-215

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A Low-Cost Cache Coherence Verification Method for Snooping Systems (Abstract)

Demid Borodin

B.H.H. (Ben) Juurlink

pp. 219-227

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Dependability Evaluation of Real Railway Interlocking Device (Abstract)

pp. 228-233

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Formulating MITF for a Multicore Processor with SEU Tolerance (Abstract)

Toshimasa Funaki

Toshinori Sato

pp. 234-241

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Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip (Abstract)

pp. 242-249

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Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs (Abstract)

Andrzej Krasniewski

pp. 250-255

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Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology (Abstract)

pp. 259-266

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Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis (Abstract)

Alberto A. Del Barrio

pp. 267-273

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Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing (Abstract)

pp. 274-281

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Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? (Abstract)

Sudip Roy

Ajit Pal

pp. 282-289

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Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations (Abstract)

Sharareh ZamanZadeh

Mohammad Mirza-Aghatabar

pp. 290-297

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Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits (Abstract)

pp. 298-303

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Leveraging Data Promotion for Low Power D-NUCA Caches (Abstract)

pp. 307-316

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Revisiting the Cache Effect on Multicore Multithreaded Network Processors (Abstract)

Jia Yu

Bin Liu

pp. 317-324

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Using Empirical Science to Engineer Systems: Optimizing Cache for Power and Performance (Abstract)

pp. 325-333

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Reducing Leakage through Filter Cache (Abstract)

Roberto Giorgi

Paolo Bennati

pp. 334-341

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Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures (Abstract)

pp. 345-352

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Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications (Abstract)

pp. 353-359

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Virtual Scan Chains for Online Testing of FPGA-based Embedded Systems (Abstract)

pp. 360-366

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Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication (Abstract)

pp. 367-372

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Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools (Abstract)

Maurizio Tranchero

Leonardo M. Reyneri

pp. 373-380

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PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems (Abstract)

pp. 383-390

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Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism (Abstract)

pp. 391-398

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Digital Nuclear Magnetic Resonance Acquisition Channel (Abstract)

pp. 399-404

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Fast FPGA-based Trigger and Data Acquisition System for the CERN Experiment NA62: Architecture and Algorithms (Abstract)

pp. 405-412

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A Novel Digital Ultrasound System for Experimental Research Activities (Abstract)

E. Boni

pp. 413-417

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A Parallel and Modular Architecture for 802.16e LDPC Codes (Abstract)

pp. 418-421

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WirelessUSB ? Performance Analysis of an Embedded System in a Peer-to-Peer Application (Abstract)

pp. 422-426

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Design of a Distributed Embedded System for Domotic Applications (Abstract)

pp. 427-431

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An Embedded Acquisition System for Remote Monitoring of Tire Status in F1 Race Cars through Thermal Images (Abstract)

pp. 432-437

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Design of a High Performance Traffic Generator on Network Processor (Abstract)

pp. 438-441

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Implementation of Microprogrammed Hard Disk Drive Servo Sequencer (Abstract)

pp. 442-446

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Quantum-Dot Cellular Automata Serial Comparator (Abstract)

pp. 447-452

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Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization (Abstract)

pp. 455-463

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Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits (Abstract)

Pedro L. Garc?a-Repetto

pp. 464-471

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Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm (Abstract)

pp. 472-479

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Technology Library Modelling for Information-driven Circuit Synthesis (Abstract)

Lech J?zwiak

Szymon Bieganski

pp. 480-489

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Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics (Abstract)

pp. 490-493

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A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis (Abstract)

George Economakos

Sotiris Xydis

pp. 494-499

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A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks (Abstract)

pp. 503-511

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A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance (Abstract)

pp. 512-519

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Exploiting WSN for Audio Surveillance Applications: The VoWSN Approach (Abstract)

pp. 520-524

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Code Generation from Statecharts: Simulation of Wireless Sensor Networks (Abstract)

Marcello Mura

Maria Giovanna Sami

pp. 525-532

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Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking (Abstract)

pp. 535-541

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Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking (Abstract)

pp. 542-549

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How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design (Abstract)

G. Paci

pp. 550-557

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An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty (Abstract)

pp. 558-565

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SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation (Abstract)

A. Neslin Ismailoglu

Murat Askar

pp. 566-571

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VLSI Implementation of a Cryptography-Oriented Reconfigurable Array (Abstract)

pp. 575-583

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A New Array Fabric for Coarse-Grained Reconfigurable Architecture (Abstract)

Yoonjin Kim

Rabi N. Mahapatra

pp. 584-591

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Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration (Abstract)

pp. 592-598

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System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments (Abstract)

pp. 599-605

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IRIS: A Firmware Design Methodology for SIMD Architectures (Abstract)

Rui Dai

pp. 609-617

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Measurement, Analysis and Modeling of RTOS System Calls Timing (Abstract)

Carlo Brandolese

William Fornaciari

pp. 618-625

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Development of Functional Delay Tests (Abstract)

pp. 626-632

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Application Analysis for Parallel Processing (Abstract)

pp. 633-640

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Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration (Abstract)

pp. 641-644

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Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor (Abstract)

pp. 645-650

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Exploring ISS Abstractions for Embedded Software Design (Abstract)

pp. 651-655

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Gianmarco De Francisci Morales

High Performance Computing for Embedded System Design: A Case Study (Abstract)

Vincenzo Catania

Alessandro G. Di Nuovo

Maurizio Palesi

Davide Patti

pp. 656-659

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Automatic Identification of Parallelism in Handel-C (Abstract)

pp. 660-664

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A Variable Length Vector Pipeline Architecture Design Methodology (Abstract)

Takashi Kambe

Makoto Saituji

pp. 665-668

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Ultra-Low Power Passive UHF RFID for Wireless Sensor Networks (Abstract)

A. Vaz

pp. 671-675

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Models and Tradeoffs in WSN System-Level Design (Abstract)

Simone Campanoni

William Fornaciari

pp. 676-684

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Pearson?based Analysis of Positioning Error Distribution in Wireless Sensor Networks (Abstract)

pp. 685-692

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On the Need for Passive Monitoring in Sensor Networks (Abstract)

pp. 693-699

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Efficient Test Pattern Compression Method Using Hard Fault Preferring (Abstract)

Jiri Jenicek

pp. 703-708

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Digital Implementation of a BIST Method based on Binary Observations (Abstract)

pp. 709-713

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Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification (Abstract)

pp. 714-720

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Power Conscious RTL Test Scheduling (Abstract)

pp. 721-728

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Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC (Abstract)

pp. 729-734

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Functional Verification of a USB Host Controller (Abstract)

Primoz Puhar

Andrej Zemva

pp. 735-740

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An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra (Abstract)

pp. 743-751

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On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components (Abstract)

H.T. Vergos

D. Bakalis

pp. 752-759

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A New Rounding Algorithm for Variable Latency Division and Square Root Implementations (Abstract)

D. Piso

J.D. Bruguera

pp. 760-767

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An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences (Abstract)

Pedro Miguens Matutino

Leonel Sousa

pp. 768-775

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Logic Transformations by Multiple Wire Network Addition (Abstract)

pp. 779-786

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On Projecting Sums of Products (Abstract)

pp. 787-794

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On Lookup Table Cascade-Based Realizations of Arbiters (Abstract)

Petr Mikusek

Vaclav Dvorak

pp. 795-802

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A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits (Abstract)

pp. 803-806

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A Wireless Sensor Platform for Assistive Technology Applications (Abstract)

pp. 809-816

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Reliable Data Transmission over Simple Wireless Channels: A Case Study (Abstract)

pp. 817-824

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A Long-term Wearable Vital Signs Monitoring System using BSN (Abstract)

D.G. Guo

Francis E.H. Tay

L. Xu

L.M. Yu

M.N. Nyan

F.W. Chong

K.L. Yap

B. Xu

pp. 825-830

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Design of an Ultra Low-Power RFID Baseband Processor Featuring an AES Cryptography Engine (Abstract)

pp. 831-838

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Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard (Abstract)

pp. 839-843

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Architecture of a Power-Gated Wireless Sensor Node (Abstract)

pp. 844-849

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A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors (Abstract)

Paris Kitsos

George Selimis

Odysseas Koufopavlou

Athanassios N. Skodras

pp. 850-853

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Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool (Abstract)

Morteza Damavandpeyma

Siamak Mohammadi

pp. 857-864

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TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path (Abstract)

Josef Strnadel

pp. 865-872

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Embedded Diagnostic Logic Test Exploiting Regularity (Abstract)

H.T. Vierhaus

R. Kothe

pp. 873-879

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On the Complexity of Error Detection Functions for Redundant Residue Number Systems (Abstract)

Tsutomu Sasao

Yukihiro Iguchi

pp. 880-887

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Programmable Numerical Function Generators for Two-Variable Functions (Abstract)

pp. 891-898

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SIMD Enhancements for a Hough Transform Implementation (Abstract)

pp. 899-903

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Hardware-oriented Adaptation of a Particle Swarm Optimization Algorithm for Object Detection (Abstract)

pp. 904-911

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Acceleration of Smith-Waterman using Recursive Variable Expansion (Abstract)

pp. 915-922

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Maximizing Resource Utilization by Slicing of Superscalar Architecture (Abstract)

Shruti Patil

Venkatesan Muthukumar

pp. 923-930

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Author Index (PDF)

pp. 931-936

Roster Page (PDF)

pp. 938