Nowadays, designing systems using soft-core processors on FPGA is gaining in popularity and methodologies must arise to fulfill this new reality. This paper presents different techniques to develop Instruction Set Simulators and its supportive components with SystemC to enable a fast FPGA development methodology without totally sacrificing the accuracy of the simulation. We have developed the Xilinx Microblaze software environment using ESL concepts at different abstractions to explore cycle accuracy versus simulation performance trade-offs. Results show that the low-level ESL model, while slower, is 6.8 times more accurate on average than the high-level model and as close as 3% from an on-FPGA execution. Conclusion tells us that a high-level model is thus appropriate for fast prototyping and debugging, while a lower-level model is more appropriate for performance estimation.