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2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links
September 03-September 05
ISBN: 978-0-7695-3277-6
| ASCII Text | x | ||
| Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania, "Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links," 2012 15th Euromicro Conference on Digital System Design, pp. 18-25, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008. | |||
| BibTex | x | ||
| @article{ 10.1109/DSD.2008.26, author = {Dario Frazzetta and Giuseppe Dimartino and Maurizio Palesi and Shashi Kumar and Vincenzo Catania}, title = {Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links}, journal ={2012 15th Euromicro Conference on Digital System Design}, volume = {0}, year = {2008}, isbn = {978-0-7695-3277-6}, pages = {18-25}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2008.26}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 15th Euromicro Conference on Digital System Design TI - Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links SN - 978-0-7695-3277-6 SP18 EP25 A1 - Dario Frazzetta, A1 - Giuseppe Dimartino, A1 - Maurizio Palesi, A1 - Shashi Kumar, A1 - Vincenzo Catania, PY - 2008 KW - routing KW - network on chip KW - fault tolerance KW - performance analysis KW - power analysis KW - architecture VL - 0 JA - 2012 15th Euromicro Conference on Digital System Design ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DSD.2008.26
In this paper we propose a series of efficient routing strategies to effectively utilize NoC systems with partially faulty links. These strategies try to use partially faulty links when the load is high and distribute traffic uniformly on links. Evaluation of our strategies for 8x8 mesh with 7% partially faulty links shows that, using our best strategy, it is possible to achieve an average reduction of up to 50% on packet delay when the load is high. We have also worked out complete designs of routers which can tolerate partial link faults and implement our routing strategies. Approximately 25% extra area and 5% extra power consumption is required for the design of the upgraded router incorporating link fault tolerance and the best routing strategy. However, the overall performance improvement counter balances such overhead resulting in an overall saving in energy consumption of up to 20%. The proposed strategies offer a way to increase the effective yield of large and complex NoC systems.
Index Terms:
routing, network on chip, fault tolerance, performance analysis, power analysis, architecture
Citation:
Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania, "Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links," dsd, pp.18-25, 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, 2008
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