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8th Euromicro Conference on Digital System Design (DSD'05)
Porto, Portugal
August 30-September 03
ISBN: 0-7695-2433-8
Table of Contents
Introduction
Cover
Keynote Speeches
SoC Design for Advanced Applications, Challenges and Perspectives
Networks on Chip
SS2: Dependability and Testing of Digital Systems, Part 1. (S1)
Milos Krstic, IHP, Im Technologiepark
Eckhard Grass, IHP, Im Technologiepark
pp. 10-16
Tun Li, National University of Defense Technology, China
Yang Guo, National University of Defense Technology, China
GongJie Liu, National University of Defense Technology, China
SiKun Li, National University of Defense Technology, China
pp. 17-25
System Synthesis, Part 1. Power and Component Driven System Synthesis (S2)
A. Cuccuru, LIFL,Lille FR.
R. De Simone, INRIA, Sophia
T. Saunier, Thales, LJS
G. Siegel, Esterel Technologies
Y. Sorel, INRIA, Rocquencourt
pp. 26-33
Circuits Synthesis, Part 1. Arithmetic (S3)
SS2: Dependability and Testing of Digital Systems, Part 2. (S4)
Jaan Raik, Tallinn University of Technology
Peeter Ellervee, Tallinn University of Technology
Valentin Tihhomirov, Tallinn University of Technology
Raimund Ubar, Tallinn University of Technology
pp. 72-78
Joachim Sudbrock, Darmstadt University of Technology
Jaan Raik, Tallinn University of Technology
Raimund Ubar, Tallinn University of Technology
Wiezlaw Kuzmicz, Warsaw University of Technology
Witold Pleskacz, Warsaw University of Technology
pp. 79-82
Zhiyuan He, Linkoping University, Sweden
Gert Jervan, Linkoping University, Sweden
Zebo Peng, Linkoping University, Sweden
Petru Eles, Linkoping University, Sweden
pp. 83-87
System Synthesis, Part 2. Component Based System Synthesis (S5)
N. Abdelli, Thalles Communication
P. Bomel, LESTER Laboratory
E. Casseau, LESTER Laboratory
AM Foulliart, Thalles Communication
C. Jego, GET/ENST
P. Kaiffasz, Thalles Communication
B. Le Gal, LESTER Laboratory
N Le Heno, Turbo Concept SAS, FRANCE
pp. 88-95
P. Bomel, LESTER Laboratory
N. Abdelli, Thalles Communication
E. Martin, LESTER Laboratory
A-M. Fouilliart, Thalles Communication
E. Boutillon, LESTER Laboratory
P. Kaifasz, Thalles Communication
pp. 96-101
Soujanna Sarkar, DSPS Group, Texas Instruments, Banglore, India
Subash G. Chandar, DSPS Group, Texas Instruments, Banglore, India
pp. 108-113
Circuits Synthesis, Part 2. Logic Synthesis (S6)
Dariusz Kania, Silesian University of Technology
Jozef Kulisz, Silesian University of Technology
Adam Milik, Silesian University of Technology
pp. 114-121
Robert Czerwinski, Institute of Electronics, Silesian University of Technology
Dariusz Kania, Institute of Electronics, Silesian University of Technology
pp. 127-134
Vladimir Ciric, Faculty of Electronic Engineering, University of Nis, Serbia and Montenegro
Ivan Milentijevic, Faculty of Electronic Engineering, University of Nis, Serbia and Montenegro
pp. 135-138
SS1: Wireless Sensor Systems, Part 1. (S7)
Panu Hamalainen, Tampere University of Technology / Institute of Digital and Computer Systems
Jari Heikkinen, Tampere University of Technology / Institute of Digital and Computer Systems
Marko Hannikainen, Tampere University of Technology / Institute of Digital and Computer Systems
Timo D. Hamalainen, Tampere University of Technology / Institute of Digital and Computer Systems
pp. 144-152
C. Siu, University of Alberta
S. Kasnavi, University of Alberta
K. Iniewski, University of Alberta
F. Nabki, University of Alberta
pp. 153-160
Petri Kukkala, Institute of Digital and Computer Systems
Marko Hannikainen, Institute of Digital and Computer Systems
Timo D. Hamalainen, Institute of Digital and Computer Systems
pp. 161-164
S. Jayapal, Institute of Microsystem Technology-IMTEK
S. Ramachandran, Institute of Microsystem Technology-IMTEK
R. Bhutada, Institute of Microsystem Technology-IMTEK
Y. Manoli, Institute of Microsystem Technology-IMTEK
pp. 165-169
Verification Techniques, Part 1. (S8)
Tun Li, National University of Defense Technology, China
Dan Zhu, National University of Defense Technology, China
Yang Guo, National University of Defense Technology, China
GongJie Liu, National University of Defense Technology, China
SiKun Li, National University of Defense Technology, China
pp. 176-183
Francisco Duarte, Universidade do Porto, INESC Porto
J. Machado da Silva, Universidade do Porto, INESC Porto
Jose C. Alves, Universidade do Porto, INESC Porto
G. A. Pinho, Universidade do Porto, INESC Porto
Jose S. Matos, Universidade do Porto, INESC Porto
pp. 184-191
E. Bareisa, Kaunas University of Technology
V. Jusas, Kaunas University of Technology
K. Motiejunas, Kaunas University of Technology
R. Seinauskas, Kaunas University of Technology
pp. 192-195
Daniel Karlson, Linkoping Universitet, Sweden
Petru Eles, Linkoping Universitet, Sweden
Zebo Peng, Linkoping Universitet, Sweden
pp. 196-201
Application Specific Architectures, Part 1. (S9)
Luciano Volcan Agostini, GME/UFRGS - GACI/UFPel - Brazil
Roger Carvalho Porto, GACI/UFPel - Brazil
Sergio Bampi, GME/UFRGS - Porto Alegre - Brazil
Ivan Saraiva Silva, DIMAp/UFRN Natal - Brazil
pp. 210-213
S. Vitabile, I.CA.R. - Italian National Research Council
V. Conti, University of Palermo
F. Gennaro, University of Palermo
F. Sorbello, University of Palermo
pp. 218-222
Hamid Safizadeh, Amirkabir University of Technology
Hamid Noori, Amirkabir University of Technology
Mehdi Sedighi, Amirkabir University of Technology
Ali Jahanian, Amirkabir University of Technology
Neda Zolfaghari, Amirkabir University of Technology
pp. 227-230
O. Cadenas, The University of Reading,
G. Megson, The University of Reading
D. Jones, The University of Reading
pp. 235-238
Stanley Hyduke, Aldec Inc, USA
Vladimir Hahanov, Kharkov National University of Radio Electronics
Volodymyr Obrizan, Kharkov National University of Radio Electronics
Olesya Guz, Kharkov National University of Radio Electronics
pp. 239-242
Zhaojun Wo, University of Massachusetts
Israel Koren, University of Massachusetts
Maciej J. Ciesielski, University of Massachusetts
pp. 247-253
SS1: Wireless Sensor Systems, Part 2. (S10)
Kashif Virk, Technical University of Denmark
Jan Madsen, Technical University of Denmark
Andreas Vad Lorentzen, Technical University of Denmark
Martin Leopold, Copenhagen University
Phillipe Bonnet, Copenhagen University
pp. 254-260
Y. Ghiassi, Sharif University of Technology
Mohammad M. M. Rad, Sharif University of Technology
Mohammad S Nikjoo, Sharif University of Technology
Ali hesam Mohseni, Sharif University of Technology
Babak H. Khalaj, Sharif University of Technology
pp. 261-266
Mikko Kohvakka, Tampere University of Technology
Marko Hannikainen, Tampere University of Technology
Timo D. Hamalainen, Tampere University of Technology
pp. 267-275
Verification Techniques, Part 2. (S11)
M?ria Fischerov?, Institute of Informatics, Slovak Academy of Sciences
Martin Simlast?, Institute of Informatics, Slovak Academy of Sciences
pp. 276-281
Miguel Pereira, Intelsis Sistemas Inteligentes, S.A.
Enrique Soto, Department of Electronic Technology, University of Vigo, Spain
Juan J. Rodr?guez-Andina, Department of Electronic Technology, University of Vigo, Spain
F.Javier Gonz?lez-Casta?, Department of Telematic Engineering, University of Vigo, Spain
pp. 282-288
Application Specific Architectures, Part 2. (S12)
Pedro Trancoso, Department of Computer Science, University of Cyprus
Maria Charalambous, Department of Computer Science, University of Cyprus
pp. 306-313
Kenneth B. Kent, University of New Brunswick
Sharon Van Schaick, University of New Brunswick
Jacqueline E. Rice, University of Lethbridge
Patricia A. Evans, University of Lethbridge
pp. 314-321
System Synthesis, Part 3. High Level Language based System Synthesis (S13)
Sergio Saponara, DIIEIT, University of Pisa
Michele Cassiano, DIIEIT, University of Pisa
Stefano Marsi, DEEI, University of Trieste
Riccardo Coen, DIIEIT, University of Pisa
Luca Fanucci, DIIEIT, University of Pisa
pp. 322-329
Reconfigurable Systems, Part 1. (S14)
Ghaffari Fakhreddine, University of Nice Sophia Antipolis
Michel Auguin, University of Nice Sophia Antipolis
Abid Mohamed, Research unit GMS, National School of Engineering of Sfax
Benjemaa Maher, Research unit GMS, National School of Engineering of Sfax
pp. 379-382
Data Management in SoC, Part 1. (S15)
Sander Stuijk, Eindhoven University of Technology
Twan Basten, Eindhoven University of Technology
Bart Mesman, Eindhoven University of Technology
Marc Geilen, Eindhoven University of Technology
pp. 388-396
F. Rivera, Autom?tica, Universidad Complutense
M. Fernandez, Autom?tica, Universidad Complutense
N. Bagherzadeh, University of California, Irvine
pp. 396-402
Anders Larsson, Linkopings Universitet
Erik Larsson, Linkopings Universitet
Petru Eles, Linkopings Universitet
Zebo Peng, Linkopings Universitet
pp. 403-411
SS3: Remonte Educational Tools for Design and Testing, Part 1 (S16)
A. Jutman, Tallinn University of Technology
J. Raik, Tallinn University of Technology
R. Ubar, Tallinn University of Technology
V. Vislogubov, Tallinn University of Technology
pp. 412-419
Josef Stmadel, Brno University of Technology, Czech Republic
Zdenek Kotasek, Brno University of Technology, Czech Republic
pp. 420-427
Oystein Gjermundnes, Department of Electronics and Telecommunications, NTNU
Einar J. Aas, Department of Electronics and Telecommunications, NTNU
pp. 428-434
V. Nelayev, Belarusian State University of Informatics and Radioelectronics, BELARUS
V. Stempitsky, Belarusian State University of Informatics and Radioelectronics, BELARUS
K. Kudin, Belarusian State University of Informatics and Radioelectronics, BELARUS
pp. 435-441
Circuits Synthesis, Part 3. Advanced Logic Synthesis (S17)
Dariusz Kania, Institute of Electronics, Silesian University of Technology
Adam Milik, Institute of Electronics, Silesian University of Technology
Józef Kulisz, Institute of Electronics, Silesian University of Technology
pp. 442-449
Mariusz Rawski, Warsaw University of Technology
Pawe Tomaszewicz, Warsaw University of Technology
Henry Selvaraj, University of Nevada, Las Vegas
Tadeusz Luba, Warsaw University of Technology
pp. 460-466
Tsutomu Sasao, Kyushu Institute of Technology
Yukihiro Iguchi, Meiji University
Takahiro Suzuki, Meiji University
pp. 467-475
Performance Optimization: Architecture and Tools, Part 1. (S18)
Danilo Pani, DIEE - University of Cagliari
Giuseppe Passino, DIEE - University of Cagliari
Luigi Raffo, DIEE - University of Cagliari
pp. 492-499
Author Index
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