|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
| ASCII Text | x | ||
| Roberto R. Osorio, Javier D. Bruguera, "A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder," 2012 15th Euromicro Conference on Digital System Design, pp. 298-305, 8th Euromicro Conference on Digital System Design (DSD'05), 2005. | |||
| BibTex | x | ||
| @article{ 10.1109/DSD.2005.9, author = {Roberto R. Osorio and Javier D. Bruguera}, title = {A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder}, journal ={2012 15th Euromicro Conference on Digital System Design}, volume = {0}, year = {2005}, isbn = {0-7695-2433-8}, pages = {298-305}, doi = {http://doi.ieeecomputersociety.org/10.1109/DSD.2005.9}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 15th Euromicro Conference on Digital System Design TI - A New Architecture for fast Arithmetic Coding in H.264 Advanced Video Coder SN - 0-7695-2433-8 SP298 EP305 A1 - Roberto R. Osorio, A1 - Javier D. Bruguera, PY - 2005 KW - null VL - 0 JA - 2012 15th Euromicro Conference on Digital System Design ER - | |||
In this work, a new architecture for binary arithmetic coding is presented in the context of the new AVC/H.264 standard for video coding. Among the new technologies included in AVC/H.264 a Context Adaptive Binary Arithmetic Coder (CABAC) is used that outperforms the baseline entropy coder in a significant manner. In this work we justify the need for a new architecture that implements the unique characteristics of CABAC that are not found in other implementations of arithmetic coding. We show that a fast architecture is needed that combines short cycle time and application-aware scheduling in order to accomplish with the high computational demands. A number of optimizations are introduced that allow processing several symbols per cycle and reduce data binarization overhead. Implementation results are shown for a Virtex-II FPGA and the main conclusions are presented.