This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Euromicro Symposium on Digital System Design (DSD'04)
Dynamic Filter Cache for Low Power Instruction Memory Hierarchy
Rennes, France
August 31-September 03
ISBN: 0-7695-2203-3
Kugan Vivekanandarajah, Nanyang Technological University, Singapore
Thambipillai Srikanthan, Nanyang Technological University, Singapore
Saurav Bhattacharyya, Nanyang Technological University, Singapore
Filter cache(FC) is effective in achieving energy saving at the expense of some performance degradation. The energy savings, here, comes from repeated execution of tiny loops from energy efficient FC. The absence of cacheable loops leads to performance degradation in such FC structures. Therefore, we propose a simple dynamic FC scheme, which detects the opportunity for use of the FC and enables (or disables) it dynamically. Thus providing (slightly reduced) energy savings at minimal performance degradation. A combination of the predictive filter cache with the above schemes reduces the performance and energy penalty. For the benchamrks simulated with 256 Byte FC, the average performance degradation is 1.13% with the proposed scheme compared to 2.47% with just the predictive filter cache. With the same configuration, the resulting energy reduction is 42.77%. Finally, the proposed dynamic filter cache scheme is inherently simple and hence it lends well for VLSI efficient implementation.
Citation:
Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya, "Dynamic Filter Cache for Low Power Instruction Memory Hierarchy," dsd, pp.607-610, Euromicro Symposium on Digital System Design (DSD'04), 2004
Usage of this product signifies your acceptance of the Terms of Use.