CSDL - Proceedings D

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Conference Committees (PDF)

pp. xii

Systems Are Made from Transistors: UDSM Technology Creates New Challenges for Library and IC Development (PDF)

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Plenary — Keynote Session I

Ulf Schlichtmann, Infineon Technologies AG

pp. 2

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Processor and Memory Architectures

An Asynchronous Victim Cache (Abstract)

D. Hormdee, University of Manchester

J. D. Garside, University of Manchester

S. B. Furber, University of Manchester

pp. 4

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Formal Verification of a DSP Chip Using an Iterative Approach (Abstract)

Ali Habibi, Concordia University

Sofiène Tahar, Concordia University

Adel Ghazel, ?cole Superieure Des Communications de Tunis

pp. 12

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Hardware Architecture for Java in a Hardware/Software Co-Design of the Virtual Machine (Abstract)

Kenneth B. Kent, University of Victoria

Micaela Serra, University of Victoria

pp. 20

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Enhanced Configurable Parallel Memory Architecture (Abstract)

Jarno Vanne, Tampere University of Technology

Eero Aho, Tampere University of Technology

Kimmo Kuusilinna, Tampere University of Technology

Timo Hämäläinen, Tampere University of Technology

pp. 28

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Partitioning and Decomposition

Recursive Bi-Partitioning of Netlists for Large Number of Partitions (Abstract)

R. Drechsler, University of Bremen

W. Günther, Infineon Technologies

T. Eschbach, Albert-Ludwigs-University

L. Linhard, Concept Engineering GmbH

G. Angst, Concept Engineering GmbH

pp. 38

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Folded Bit-Plane FIR Filter Architecture with Changeable Folding Factor (Abstract)

Ivan Milentijević, University of Niš

Vladimir Ćirić, University of Niš

Teufik Tokić, University of Niš

Oliver Vojinović, University of Niš

pp. 45

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Best Polarity for Low Power XOR Gate Decomposition (Abstract)

Yinshui Xia, Napier University

A. E. A. Almaini, Napier University

pp. 53

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A Hybrid Evolutionary Algorithm for Multi-FPGA Systems Design (Abstract)

J.I. Hidalgo, Universidad Complutense de Madrid

J. Lanchares, Universidad Complutense de Madrid

A. Ibarra, Universidad Complutense de Madrid

R. Hermida, Universidad Complutense de Madrid

pp. 60

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Special Architectures

A Flexible Architecture for H.263 Video Coding (Abstract)

Matias J. Garrido, Universidad Politécnica de Madrid

César Sanz, Universidad Politécnica de Madrid

Marcos Jiménez, Universidad Politécnica de Madrid

Juan M. Meneses, Universidad Politécnica de Madrid

pp. 70

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The Synthesis of a Hardware Scheduler for Non-Manifest Loops (Abstract)

Omar Mansour, University of Twente

Egbert Molenkamp, University of Twente

Thijs Krol, University of Twente

pp. 78

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Configurable Memory Organisation for Communication Applications (Abstract)

Juha-Pekka Soininen, Technical Research Centre of Finland

Antti Pelkonen, Technical Research Centre of Finland

Jussi Roivainen, Technical Research Centre of Finland

pp. 86

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Enhanced Reusability for SoC-Based HW/SW Co-Design (Abstract)

Maik Boden, FhG IIS Erlangen

Jörg Schneider, FhG IIS Erlangen

Klaus Feske, FhG IIS Erlangen

Steffen Rülke, FhG IIS Erlangen

pp. 94

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System Specification and Modelling

Integrating a Computational Model and a Run Time System for Image Processing on a UAV (Abstract)

Per Andersson, Lunds University

Krzysztof Kuchcinski, Lunds University

Klas Nordberg, Link?ping University

Patrick Doherty, Link?ping University

pp. 102

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Specification and Simulation of Microprocessor Operations and Parallel Instructions (Abstract)

Loe Feijs, Eindhoven University of Technology

Paul Gorissen, Philips Research Laboratories Eindhoven

Joachim Trescher, Philips Research Laboratories Eindhoven

pp. 110

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Rapid Prototyping of Mixed Hardware and Software Systems (Abstract)

Martyn Edwards, UMIST

Benjamin Fozard, UMIST

pp. 118

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Integration of Instruction Set Simulators into SystemC High Level Models (Abstract)

Ilia Oussorov, Infineon Technologies AG

Wolfgang Raab, Infineon Technologies AG

Ulrich Hachmann, Infineon Technologies AG

Alex Kravtsov, Infineon Technologies AG

pp. 126

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Parallel Processor Architectures

Architecture Design of a Scalable Single-Chip Multi-Processor (Abstract)

B. D. Theelen, Eindhoven University of Technology

A. C. Verschueren, Eindhoven University of Technology

pp. 132

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Parallel Multimedia Processor Using Customised Infineon TriCores (Abstract)

Ari Wahyudi, Nanyang Technological University

Amos Omondi, Nanyang Technological University

pp. 140

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Improving the Operation Autonomy of SIMD Processing Elements by Using Guarded Instructions and Pseudo Branches (Abstract)

Manuel Lois Anido, Federal University of Rio de Janeiro

Alexander Paar, Universit?t Karlsruhe

Nader Bagherzadeh, University of California at Irvine

pp. 148

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Implementation of a Streaming Execution Unit (Abstract)

Dmitry Cheresiz, Leiden University

Ben Juurlink, Delft University of Technology

Stamatis Vassiliadis, Delft University of Technology

Harry A.G. Wijshoff, Leiden University

pp. 156

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Verification and Test

Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level (Abstract)

Josef Strnadel, Brno University of Technology

Zdeněk Kotásek, Brno University of Technology

pp. 166

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Fault Latencies of Concurrent Checking FSMs (Abstract)

Roman Goot, Academic Technological Institute

Ilya Levin, Tel Aviv University

Sergei Ostanin, Tel Aviv University

pp. 174

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Using Formal Tools to Study Complex Circuits Behaviour (Abstract)

Paul Amblard, TIMA-CMP

Fabienne Lagnier, Vérimag

Michel Lévy, LSR-IMAG

pp. 180

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Integrated Design and Test Generation Under Internet Based Environment MOSCITO (Abstract)

A. Schneider, Fraunhofer Institute for Integrated Circuits

K.-H. Diener, Fraunhofer Institute for Integrated Circuits

E. Ivask, Tallinn Technical University

R. Ubar, Tallinn Technical University,

E. Gramatova, Institute of Informatics

T. Hollstein, Technical University of Darmstadt

W. Kuzmicz, Warsaw University of Technology

Z. Peng, Link?ping University

pp. 187

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Plenary — Keynote Session II

Networks on Silicon: Blessing or Nightmare? (Abstract)

Paul Wielage, Philips Research Laboratories

Kees Goossens, Philips Research Laboratories

pp. 196

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Embedded Software: How To Make It Efficient? (Abstract)

Peter Marwedel, Universität Dortmund

pp. 201

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Filter and Arithmetic Circuits

A Design for a Low-Power Digital Matched Filter Applicable to W-CDMA (Abstract)

Shoji Goto, SANYO Electric Co., Ltd.

Takashi Yarnada, SANYO Electric Co., Ltd.

Norihisa Takayarna, SANYO Electric Co., Ltd.

Yoshifurni Matsushita, SANYO Electric Co., Ltd.

Yasoo Harada, SANYO Electric Co., Ltd.

Hiroto Yasuura, Kyushu University

pp. 210

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Analysis of the Impact of Different Methods for Division/Square Root Computation in the Performance of a Superscalar Microprocessor (Abstract)

D. Piso, Universidad Santiago de Compostela

J. A. Piñeiro, Universidad Santiago de Compostela

J. D. Bruguera, Universidad Santiago de Compostela

pp. 218

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Reconfigurable Hardware Implementation of Montgomery Modular Multiplication and Parallel Binary Exponentiation (Abstract)

Nadia Nedjah, State University of Rio de Janeiro

Luiza de Macedo Mourelle, State University of Rio de Janeiro

pp. 226

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Circuit Synthesis and Optimisation

Decision Diagram Optimization Using Copy Properties (Abstract)

Dragan Janković, University of Niš

Radomir S. Stanković, University of Niš

Rolf Drechsler, University of Bremen

pp. 236

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Use of the Autocorrelation Function in the Classification of Switching Functions (Abstract)

J. E. Rice, University of Victoria

J. C. Muzio, University of Victoria

pp. 244

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Optimization of Equational Specifications Using Genetic Techniques (Abstract)

A. Ibarra, Universidad Complutense Madrid

J. M. Mendías, Universidad Complutense Madrid

J. Lanchares, Universidad Complutense Madrid

J. I. Hidalgo, Universidad Complutense Madrid

R. Hermida, Universidad Complutense Madrid

pp. 252

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Synthesis of Multipurpose Reversible Logic Gates (Abstract)

Pawel Kerntopf, Warsaw University of Technology

pp. 259

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Reconfigurable Computing Architectures

Performance of Remote FPGA-Based Coprocessors for Image-Processing Applications (Abstract)

Domingo Benitez, University of Las Palmas G.C.

pp. 268

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Improving mW/MHz Ratio in FPGAs Pipelined Designs (Abstract)

Oswaldo Cadenas, University of Reading

Graham Megson, University of Reading

pp. 276

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Design of an FPGA Based Adaptive Neural Controller for Intelligent Robot Navigation (Abstract)

M. A. Hannan Bin Azhar, University of Kent

K. R. Dimond, University of Kent

pp. 283

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Constant Coefficient Convolution Implemented in FPGAs (Abstract)

Ernest Jamro, AGH Technical University of Cracow

Kazimierz Wiatr, AGH Technical University of Cracow

pp. 291

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An Evaluation of an FPGA Run-Time Support System (Abstract)

P. Green, UMIST

M. Vakondios, UMIST

M. Edwards, UMIST

pp. 299

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High Level Synthesis

Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis (Abstract)

J. M. Mendías, Universidad Complutense de Madrid

R. Hermida, Universidad Complutense de Madrid

M. C. Molina, Universidad Complutense de Madrid

O. Peñalba, Universidad Complutense de Madrid

pp. 308

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An Efficient List-Based Scheduling Algorithm for High-Level Synthesis (Abstract)

Azeddien M. Sllame, Brno University of Technology

Vladimir Drabek, Brno University of Technology

pp. 316

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Source Code Transformation to Improve Conditional Hardware Reuse (Abstract)

0. Peñalba, Universidad Complutense de Madrid

J. M. Mendias, Universidad Complutense de Madrid

R. Hermida, Universidad Complutense de Madrid

pp. 324

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Work Out of the Algorithm Based on A-Mod for Detection Borderlines in Images Provided by the Intravascular Ultrasound System (IVUS) with 64 Transducers (Abstract)

Poster Session

Željko Vujović, School of Electrotechnic

pp. 332

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Reachability Analysis for Formal Verification of SystemC (Abstract)

Rolf Drechsler, University of Bremen

Daniel Große, Albert-Ludwigs-University

pp. 337

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Simplifying Instruction Issue Logic in Superscalar Processors (Abstract)

Toshinori Sato, Kyushu Institute of Technology

Itsujiro Arita, Kyushu Institute of Technology

pp. 341

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A Self-Timed Arithmetic Unit for Elliptic Curve Cryptography (Abstract)

Martin Feldhofer, Graz University of Technology

Thomas Trathnigg, Graz University of Technology

Bernd Schnitzer, Graz University of Technology

pp. 347

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Low Power Strategy for a TFT Controller (Abstract)

Giuseppe Notarangelo, STMicroelectronics

Marco Gibilaro, STMicroelectronics

Francesco Pappalardo, STMicroelectronics

Agatino Pennisi, STMicroelectronics

Gaetano Palumbo, University of Catania

pp. 351

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Hardware Implementation of a Memory Allocator (Abstract)

Khushwinder Jasrotia, University of Toronto

Jianwen Zhu, University of Toronto

pp. 355

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Evolutionary Algorithm for State Assignment of Finite State Machines (Abstract)

Mariusz Chyży, Polish-Japanese Institute of Information Technology

Witold Kosiński, Polish-Japanese Institute of Information Technology

pp. 359

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Specification and Modelling

Use of HDL Code Checkers to Support the IP Entrance Check — A Requirement Analysis (Abstract)

Ronny Frevert, FhG IIS, EAS Dresden

Steffen Rülke, FhG IIS, EAS Dresden

Torsten Schäfer, FhG IIS, EAS Dresden

Frank Dresig, AMD Saxony Manufacturing GmbH

pp. 364

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On the Fundamental Design Gap in Terabit per Second Packet Switching (Abstract)

M. Verhappen, IBM Research, Zurich Research Laboratory

P. H. A. van der Putten, Eindhoven University of Technology

J. P. M. Voeten, Eindhoven University of Technology

pp. 371

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Synthesis and Algorithms

Speeding up Elliptic Cryptosystems Using a New Signed Binary Representation for Integers (Abstract)

Rajendra Katti, North Dakota State University

pp. 380

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Bit-Level Allocation of Multiple-Precision Specifications (Abstract)

M. C. Molina, Universidad Complutense de Madrid

J. M. Mendías, Universidad Complutense de Madrid

R. Hermida, Universidad Complutense de Madrid

pp. 385

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Author Index

Author Index (Abstract)

pp. 393

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