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Proceedings Euromicro Symposium on Digital System Design. DSD'2002 (2002)
Dortmund, Germany
Sept. 4, 2002 to Sept. 6, 2002
ISBN: 0-7695-1790-0
TABLE OF CONTENTS
Introduction
Plenary — Keynote Session I
Processor and Memory Architectures
D. Hormdee , University of Manchester
S. B. Furber , University of Manchester
pp. 4
Ali Habibi , Concordia University
Sofiène Tahar , Concordia University
Adel Ghazel , ?cole Superieure Des Communications de Tunis
pp. 12
Eero Aho , Tampere University of Technology
Kimmo Kuusilinna , Tampere University of Technology
Timo Hämäläinen , Tampere University of Technology
pp. 28
Partitioning and Decomposition
W. Günther , Infineon Technologies
T. Eschbach , Albert-Ludwigs-University
L. Linhard , Concept Engineering GmbH
G. Angst , Concept Engineering GmbH
pp. 38
Vladimir Ćirić , University of Niš
Ivan Milentijević , University of Niš
Oliver Vojinović , University of Niš
pp. 45
Yinshui Xia , Napier University
pp. 53
J.I. Hidalgo , Universidad Complutense de Madrid
A. Ibarra , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 60
Special Architectures
César Sanz , Universidad Politécnica de Madrid
Matias J. Garrido , Universidad Politécnica de Madrid
Juan M. Meneses , Universidad Politécnica de Madrid
pp. 70
Egbert Molenkamp , University of Twente
Omar Mansour , University of Twente
pp. 78
Juha-Pekka Soininen , Technical Research Centre of Finland
Jussi Roivainen , Technical Research Centre of Finland
pp. 86
Maik Boden , FhG IIS Erlangen
Jörg Schneider , FhG IIS Erlangen
Klaus Feske , FhG IIS Erlangen
Steffen Rülke , FhG IIS Erlangen
pp. 94
System Specification and Modelling
Loe Feijs , Eindhoven University of Technology
Joachim Trescher , Philips Research Laboratories Eindhoven
pp. 110
Wolfgang Raab , Infineon Technologies AG
Ulrich Hachmann , Infineon Technologies AG
Alex Kravtsov , Infineon Technologies AG
pp. 126
Parallel Processor Architectures
B. D. Theelen , Eindhoven University of Technology
A. C. Verschueren , Eindhoven University of Technology
pp. 132
Ari Wahyudi , Nanyang Technological University
Amos Omondi , Nanyang Technological University
pp. 140
Manuel Lois Anido , Federal University of Rio de Janeiro
Alexander Paar , Universit?t Karlsruhe
Nader Bagherzadeh , University of California at Irvine
pp. 148
Dmitry Cheresiz , Leiden University
Ben Juurlink , Delft University of Technology
Stamatis Vassiliadis , Delft University of Technology
Harry A.G. Wijshoff , Leiden University
pp. 156
Verification and Test
Ilya Levin , Tel Aviv University
Sergei Ostanin , Tel Aviv University
pp. 174
K.-H. Diener , Fraunhofer Institute for Integrated Circuits
E. Ivask , Tallinn Technical University
R. Ubar , Tallinn Technical University,
E. Gramatova , Institute of Informatics
T. Hollstein , Technical University of Darmstadt
W. Kuzmicz , Warsaw University of Technology
Z. Peng , Link?ping University
pp. 187
Plenary — Keynote Session II
Paul Wielage , Philips Research Laboratories
Kees Goossens , Philips Research Laboratories
pp. 196
Peter Marwedel , Universität Dortmund
pp. 201
Filter and Arithmetic Circuits
Takashi Yarnada , SANYO Electric Co., Ltd.
Norihisa Takayarna , SANYO Electric Co., Ltd.
Yoshifurni Matsushita , SANYO Electric Co., Ltd.
Shoji Goto , SANYO Electric Co., Ltd.
Hiroto Yasuura , Kyushu University
pp. 210
D. Piso , Universidad Santiago de Compostela
J. A. Piñeiro , Universidad Santiago de Compostela
J. D. Bruguera , Universidad Santiago de Compostela
pp. 218
Circuit Synthesis and Optimisation
Dragan Janković , University of Niš
Radomir S. Stanković , University of Niš
Rolf Drechsler , University of Bremen
pp. 236
J. M. Mendías , Universidad Complutense Madrid
J. Lanchares , Universidad Complutense Madrid
J. I. Hidalgo , Universidad Complutense Madrid
R. Hermida , Universidad Complutense Madrid
pp. 252
Pawel Kerntopf , Warsaw University of Technology
pp. 259
Reconfigurable Computing Architectures
Oswaldo Cadenas , University of Reading
pp. 276
Ernest Jamro , AGH Technical University of Cracow
pp. 291
High Level Synthesis
R. Hermida , Universidad Complutense de Madrid
M. C. Molina , Universidad Complutense de Madrid
O. Peñalba , Universidad Complutense de Madrid
pp. 308
Azeddien M. Sllame , Brno University of Technology
Vladimir Drabek , Brno University of Technology
pp. 316
J. M. Mendias , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 324
Poster Session
Rolf Drechsler , University of Bremen
Daniel Große , Albert-Ludwigs-University
pp. 337
Toshinori Sato , Kyushu Institute of Technology
Itsujiro Arita , Kyushu Institute of Technology
pp. 341
Thomas Trathnigg , Graz University of Technology
Martin Feldhofer , Graz University of Technology
pp. 347
Marco Gibilaro , STMicroelectronics
Francesco Pappalardo , STMicroelectronics
Agatino Pennisi , STMicroelectronics
Gaetano Palumbo , University of Catania
pp. 351
Khushwinder Jasrotia , University of Toronto
pp. 355
Mariusz Chyży , Polish-Japanese Institute of Information Technology
pp. 359
Specification and Modelling
Ronny Frevert , FhG IIS, EAS Dresden
Steffen Rülke , FhG IIS, EAS Dresden
Torsten Schäfer , FhG IIS, EAS Dresden
Frank Dresig , AMD Saxony Manufacturing GmbH
pp. 364
M. Verhappen , IBM Research, Zurich Research Laboratory
P. H. A. van der Putten , Eindhoven University of Technology
J. P. M. Voeten , Eindhoven University of Technology
pp. 371
Synthesis and Algorithms
M. C. Molina , Universidad Complutense de Madrid
R. Hermida , Universidad Complutense de Madrid
pp. 385
Author Index
Author Index (Abstract)
pp. 393
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