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Euromicro Symposium on Digital System Design (DSD'02)
Dortmund, Germany
September 04-September 06
ISBN: 0-7695-1790-0
Table of Contents
Introduction
Plenary — Keynote Session I
Processor and Memory Architectures
D. Hormdee, University of Manchester
J. D. Garside, University of Manchester
S. B. Furber, University of Manchester
pp. 4
Ali Habibi, Concordia University
Sofiène Tahar, Concordia University
Adel Ghazel, ?cole Superieure Des Communications de Tunis
pp. 12
Jarno Vanne, Tampere University of Technology
Eero Aho, Tampere University of Technology
Kimmo Kuusilinna, Tampere University of Technology
Timo Hämäläinen, Tampere University of Technology
pp. 28
Partitioning and Decomposition
R. Drechsler, University of Bremen
W. Günther, Infineon Technologies
T. Eschbach, Albert-Ludwigs-University
L. Linhard, Concept Engineering GmbH
G. Angst, Concept Engineering GmbH
pp. 38
J.I. Hidalgo, Universidad Complutense de Madrid
J. Lanchares, Universidad Complutense de Madrid
A. Ibarra, Universidad Complutense de Madrid
R. Hermida, Universidad Complutense de Madrid
pp. 60
Special Architectures
Matias J. Garrido, Universidad Politécnica de Madrid
César Sanz, Universidad Politécnica de Madrid
Marcos Jiménez, Universidad Politécnica de Madrid
Juan M. Meneses, Universidad Politécnica de Madrid
pp. 70
Juha-Pekka Soininen, Technical Research Centre of Finland
Antti Pelkonen, Technical Research Centre of Finland
Jussi Roivainen, Technical Research Centre of Finland
pp. 86
System Specification and Modelling
Loe Feijs, Eindhoven University of Technology
Paul Gorissen, Philips Research Laboratories Eindhoven
Joachim Trescher, Philips Research Laboratories Eindhoven
pp. 110
Ilia Oussorov, Infineon Technologies AG
Wolfgang Raab, Infineon Technologies AG
Ulrich Hachmann, Infineon Technologies AG
Alex Kravtsov, Infineon Technologies AG
pp. 126
Parallel Processor Architectures
B. D. Theelen, Eindhoven University of Technology
A. C. Verschueren, Eindhoven University of Technology
pp. 132
Dmitry Cheresiz, Leiden University
Ben Juurlink, Delft University of Technology
Stamatis Vassiliadis, Delft University of Technology
Harry A.G. Wijshoff, Leiden University
pp. 156
Verification and Test
Roman Goot, Academic Technological Institute
Ilya Levin, Tel Aviv University
Sergei Ostanin, Tel Aviv University
pp. 174
A. Schneider, Fraunhofer Institute for Integrated Circuits
K.-H. Diener, Fraunhofer Institute for Integrated Circuits
E. Ivask, Tallinn Technical University
R. Ubar, Tallinn Technical University,
E. Gramatova, Institute of Informatics
T. Hollstein, Technical University of Darmstadt
W. Kuzmicz, Warsaw University of Technology
Z. Peng, Link?ping University
pp. 187
Plenary — Keynote Session II
Paul Wielage, Philips Research Laboratories
Kees Goossens, Philips Research Laboratories
pp. 196
Filter and Arithmetic Circuits
Shoji Goto, SANYO Electric Co., Ltd.
Takashi Yarnada, SANYO Electric Co., Ltd.
Norihisa Takayarna, SANYO Electric Co., Ltd.
Yoshifurni Matsushita, SANYO Electric Co., Ltd.
Yasoo Harada, SANYO Electric Co., Ltd.
Hiroto Yasuura, Kyushu University
pp. 210
Circuit Synthesis and Optimisation
A. Ibarra, Universidad Complutense Madrid
J. M. Mendías, Universidad Complutense Madrid
J. Lanchares, Universidad Complutense Madrid
J. I. Hidalgo, Universidad Complutense Madrid
R. Hermida, Universidad Complutense Madrid
pp. 252
Reconfigurable Computing Architectures
Ernest Jamro, AGH Technical University of Cracow
Kazimierz Wiatr, AGH Technical University of Cracow
pp. 291
High Level Synthesis
J. M. Mendías, Universidad Complutense de Madrid
R. Hermida, Universidad Complutense de Madrid
M. C. Molina, Universidad Complutense de Madrid
O. Peñalba, Universidad Complutense de Madrid
pp. 308
0. Peñalba, Universidad Complutense de Madrid
J. M. Mendias, Universidad Complutense de Madrid
R. Hermida, Universidad Complutense de Madrid
pp. 324
Poster Session
Martin Feldhofer, Graz University of Technology
Thomas Trathnigg, Graz University of Technology
Bernd Schnitzer, Graz University of Technology
pp. 347
Giuseppe Notarangelo, STMicroelectronics
Marco Gibilaro, STMicroelectronics
Francesco Pappalardo, STMicroelectronics
Agatino Pennisi, STMicroelectronics
Gaetano Palumbo, University of Catania
pp. 351
Mariusz Chyży, Polish-Japanese Institute of Information Technology
Witold Kosiński, Polish-Japanese Institute of Information Technology
pp. 359
Specification and Modelling
M. Verhappen, IBM Research, Zurich Research Laboratory
P. H. A. van der Putten, Eindhoven University of Technology
J. P. M. Voeten, Eindhoven University of Technology
pp. 371
Synthesis and Algorithms
M. C. Molina, Universidad Complutense de Madrid
J. M. Mendías, Universidad Complutense de Madrid
R. Hermida, Universidad Complutense de Madrid
pp. 385
Author Index
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