CSDL - Proceedings D

Conference Committees (PDF)

pp. xii

System Design-Chair: Martyn Edwards

Header Compression in Handel-C -- An Internet Application and a New Design Language (Abstract)

Kjell Torkelsson, Ericsson Radio Systems AB, Sweden, Celoxica Ltd

Johan Ditmar, Ericsson Radio Systems AB, Sweden, Celoxica Ltd

pp. 0002

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A Multi-Lingual Synthesis and Verification Environment (Abstract)

George Economakos, National Technical University of Athens

Stergios Stergiou, National Technical University of Athens

George Papakonstantinou, National Technical University of Athens

Vassilios Zoukos, INTRACOM S. A., Access and Transmission Department

pp. 0008

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A Design Methodology for High Performance IC's: Wireless Broadband Radio Baseband Case Study (Abstract)

Volker Aue, Systemonic AG

Johannes Kneip, Systemonic AG

Matthias Weiss, Systemonic AG

Michael Bolle, Systemonic AG

Gerhard Fettweis, Systemonic AG

pp. 0016

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Application of Decision-Making Method for Architecture Selection of ADSL Modem (Abstract)

Juha-Pekka Soininen, VTT Electronics

Sandrine Boumard, VTT Electronics

Tommi Salminen, VTT Electronics

Hannu Heusala, University of Oulu

pp. 0021

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Logic Synthesis-Chair: Tadeusz Luba

Effective and Efficient FPGA Synthesis through Functional Decomposition Based on Information Relationship Measures (Abstract)

L. Jozwiak, Eindhoven University of Technology

A. Chojnacki, Eindhoven University of Technology

pp. 0030

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Practical Aspects of Logic Synthesis Based on Functional Decomposition (Abstract)

Mariusz Rawski, Warsaw University of Technology, Institute of Telecommunications

Rafal Rzechowski, Warsaw University of Technology, Institute of Telecommunications

Zbigniew Jachna, Military Academy of Technology

Ireneusz Brzozowski, University of Mining and Metallurgy AGH, Institute of Electronics

pp. 0038

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Fast and Compact Sequential Circuits through the Information-Driven Circuit Synthesis (Abstract)

L. Józwiak, Eindhoven University of Technology

A. Chojnacki, Eindhoven University of Technology

A. Slusarczyk, Eindhoven University of Technology

pp. 0046

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Greedy_IIP: Partitioning Large Graphs by Greedy Iterative Improvement (Abstract)

B. Becker, Institute of Computer Science, Albert-Ludwigs-University Corporate Technology

T. Eschbach, Institute of Computer Science, Albert-Ludwigs-University Corporate Technology

R. Drechsler, Siemens AG

W. Günther, Siemens AG

pp. 0054

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Embedded Systems-Chair: Krzysztof Kuchcinski

Combining Languages in Embedded System Design (PDF)

R. Ernst

pp. 0062

Hierarchical Modeling and Verification of Embedded Systems (Abstract)

Luis Alejandro Cortés, Link?ping University

Petru Eles, Link?ping University

Zebo Peng, Link?ping University

pp. 0063

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Decision Diagrams and Synthesis-Chair: Marek Perkowski

Minimization of OPKFDDs Using Genetic Algorithms (Abstract)

M. Jung, Chonnam National University

G. Lee, Chonnam National University

S. Park, Hanyang University

R. Drechsler, Siemens, AG

pp. 0072

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An Approach to Minimization of Decision Diagrams (Abstract)

Pawel Kerntopf, Warsaw University of Technology

pp. 0079

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Synthesis of ASM-based Self-Checking Controllers (Abstract)

Ilya Levin, Tel-Aviv University

Vladimir Sinelnikov, Academic Technological Institute

Mark Karpovsky, Boston University

pp. 0087

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Two-Criterial Constraint-Driven FSM State Encoding for Low Power (Abstract)

Manfred Koegst, Fraunhofer-Institut f?r Integrierte Schaltungen

Steffen Rülke, Fraunhofer-Institut f?r Integrierte Schaltungen

Günter Franke, Hochschule f?r Technik und Wirtschaft

Maria José Avedillo, Instituto de Microelectr?nica de Sevilla

pp. 0094

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Reconfigurable Computing-Chair: Adam Postula

Reconfigurable Computing at Xilinx (PDF)

S. Guccione

pp. 0102

Reconfigurable Computing: A New Business Model and its Impact on SoC Design (Abstract)

Reiner Harenstein, University of Kaiserskautern

pp. 0103

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Reconfigurable Computing-Chair: Rolf Ernst

Design and Implementation of Reconfigurable Processor for Problems of Combinatorial Computations (Abstract)

Iouliia Skliarova, University of Aveiro

António B. Ferrari, University of Aveiro

pp. 0112

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Optimisation of PPMC Model for Hardware Implementation (Abstract)

C.Feregrino Uribe, Loughborough University

S.R. Jones, Loughborough University

pp. 0120

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Traffic Scheduling Coprocessor with Schedulability Analysis Capability (Abstract)

Ernesto Martins, University of Aveiro

José A. Fonseca, University of Aveiro

pp. 0127

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A Run-Time Support Environment for Reconfigurable Systems (Abstract)

L. Bubb, UMIST

M. Edwards, UMIST

P. Green, UMIST

C. Pimlott, UMIST

K. Rees, UMIST

M. Stewart, UMIST

A. Taylor, UMIST

M. Vakondios, UMIST

J. Yates, UMIST

pp. 0135

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Synthesis and Verification Posters-Chair: Rolf Drechsler

An Improved Input-Output Encoding Approach for Functional Decomposition (Abstract)

Muthukumar Venkatesan, University of Nevada

pp. 0144

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Level Assignment for Displaying Combinational Logic (Abstract)

Rolf Drechsler, Siemens AG Concept Engineering GmbH

Wolfgang Günther, Siemens AG Concept Engineering GmbH

Lothar Linhard, Siemens AG Concept Engineering GmbH

Gerhard Angst, Siemens AG Concept Engineering GmbH

pp. 0148

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System Modeling in the COSMA Environment (Abstract)

W. B. Daszczuk, Warsaw University of Technology

W. Grabski, Warsaw University of Technology

J. Miescicki, Warsaw University of Technology

J. Wytrebowicz, Warsaw University of Technology

pp. 0152

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Evaluation of Temporal Formulas Based on "Checking by Spheres" (Abstract)

Wiktor B. Daszczuk, Warsaw University of Technology

pp. 0158

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Applying Formal Verification with Protocol Compiler (Abstract)

Christian Stangier, University of Trier

Ulrich Holtmann, Synopsys GmbH

pp. 0165

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Synthesis of Sequential Circuits on Programmable Logic Devices Based on New Models of Finite State Machines (Abstract)

Solovjev Valeri

pp. 0170

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Processor Design-Chair: Antonio Nunez

Dynamic Branch Prediction Using Neural Networks (Abstract)

Gordon Steven, University of Hertfordshire

Rubén Anguera, University of Hertfordshire

Colin Egan, University of Hertfordshire

Fleur Steven, University of Hertfordshire

Lucian Vintan, University "Lucian Blaga" of Sibiu

pp. 0178

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Applying Caching to Two-Level Adaptive Branch Prediction (Abstract)

Colin Egan, University of Hertfordshire

Gordon B. Steven, University of Hertfordshire

Won Shim, Seoul National University of Technology

Lucian Vintan, University of Sibiu

pp. 0186

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Experimental Evaluation of CPU Performance Features (Abstract)

J. Sosnowski, Warsaw University of Technology

R. Jurkiewicz, Warsaw University of Technology

J. Nowicki, Warsaw University of Technology

pp. 0194

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A Comparison of Five Different Multiprocessor SoC Bus Architectures (Abstract)

Kyeong Keol Ryu, Georgia Institute of Technology

Eung Shin, Georgia Institute of Technology

Vincent J. Mooney, Georgia Institute of Technology

pp. 0202

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Synthesis and Test-Chair: Andrzej Krasniewski

A HW/SW Codesign Framework Based on Distributed DSP Virtual Machines (Abstract)

Christian Kreiner, Technical University Graz

Christian Steger, Technical University Graz

Egon Teiniker, Technical University Graz

Reinhold Weiss, Technical University Graz

pp. 0212

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Synthesis of Conditional Behaviors Using Hierarchical Conditional Dependency Graphs and Constraint Logic Programming (Abstract)

Krzysztof Kuchcinski, Lund University

Christophe Wolinski, IRISA, Campus Universitaire de Beaulieu

pp. 0220

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Test Generation and Fault Simulation Methods on the Basis of Cubic Algebra for Digital Devices (Abstract)

Vladimir Hahanov Anna Babich, Kharkov State Technical University of Radio Electronics

pp. 0228

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Self-Testing of User-Programmed FPGAs Based on the Concept of Linear Segments (Abstract)

Pawel Tomaszewicz, Warsaw University of Technology

Mariusz Rawski, Warsaw University of Technology

pp. 0236

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Reversible Logic-Chair: Lech J?zwiak

Fundamentals of Reversible Logic and Computing (PDF)

pp. 0244

Regular Realization of Symmetric Functions Using Reversible Logic (Abstract)

Marek Perkowski, Portland State University

Malgorzata Chrzanowska-Jeske, Portland State University

Alan Mishchenko, Portland State University

Xiaoyu Song, Portland State University

Anas Al-Rabadi, Portland State University

Bart Massey, Portland State University

Pawel Kerntopf, Technical University of Warsaw

Andrzej Buller, ATR

Lech Jozwiak, Technical University of Eindhoven

Alan Coppola, Cypress Semiconductor Northwest

pp. 0245

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Specialised Architectures-Chair: Steve Guccione

Rotating Ultrasonic Signal Vectors with a Word-Parallel CORDIC Processor (Abstract)

Andrew P. Paplinski, Monash University

Nandita Bhattacharjee, Monash University

Charles Greif, Monash University

pp. 0254

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FPGA Implementation of a Faithful Polynomial Approximation for Powering Function Computation (Abstract)

J.A. Piñeiro, University Santiago de Compostela

J.D. Bruguera, University Santiago de Compostela

J.M. Muller, CNRS

pp. 0262

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Cork Stopper Classification Using FPGAs and Digital Image Processing Techniques (Abstract)

Miguel A. Vega-Rodríguez, University de Extremadura

Juan M. Sánchez-Pérez, University de Extremadura

Juan A. Gómez-Pulido, University de Extremadura

pp. 0270

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Pipelining Considerations for an FPGA Case (Abstract)

Oswaldo Cadenas, University of Reading

Graham Megson, University of Reading

pp. 0276

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Synthesis-Chair: Adam Pawlak

Very High (Over 40 Gb/s) Speed Circuits for Optical Communications--Design Methodolgy and Application Examples (Abstract)

Agnieszka Konczykowska, OPTO+, Groupement d'Int?r?t Economique

pp. 0286

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On the Optimization Power of Redundancy Addition and Removal for Sequential Logic Optimization (Abstract)

Enrique San Millán, University Carlos III of Madrid

Luis Entrena, University Carlos III of Madrid

José Alberto Espejo, University Carlos III of Madrid

pp. 0292

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On the Use of Mutations in Boolean Minimization (Abstract)

Petr Fiser, Czech Technical University

Jan Hlavicka, Czech Technical University

pp. 0300

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Test and Design for Testability-Chair: Raimond Ubar

Evaluation of Delay Fault Testability of LUT Functions for Improved Efficiency of FPGA Testing (Abstract)

Andrzej Krasniewski, Warsaw University of Technology

pp. 0310

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Fast Test Cost Calculation for Hybrid BIST in Digital Systems (Abstract)

Elmet Orasson, Tallinn Technical University

Rein Raidma, Tallinn Technical University

Raimund Ubar, Tallinn Technical University

Gert Jervan, Link?ping University

Zebo Peng, Link?ping University

pp. 0318

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Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing (Abstract)

Simon Leung, The University of Queensland

Adam Postula, The University of Queensland

Ahmed Hemani, Spirea AB, Kista Science Park, Electrum 229

pp. 0326

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Processor Design-Chair: Janusz Sosnowski

Design of a Faithful LNS Interpolator (Abstract)

Mark G. Arnold, UMIST

pp. 0336

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Architectural Design of a Fast Floating-Point Multiplication-Add Fused Unit Using Signed-Digit Addition (Abstract)

Chichyang Chen, Feng Chia University

Liang-An Chen, Feng Chia University

Jih-Ren Cheng, Feng Chia University

pp. 0346

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High-Performance Floating Point Divide (Abstract)

Albert A. Liddicoat, Stanford University

Michael J. Flynn, Stanford University

pp. 0354

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Specialised Architectures Posters-Chair: Kjell Torkelsson

An Assesment of FPGA Suitability for Implementation of Real-Time Motion Estimation (Abstract)

Andrzej Ryszko, AGH Technical University of Cracow

Kazimierz Wiatr, AGH Technical University of Cracow

pp. 0364

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Portable Acquisition System for Measurements of Pressures, Temperatures and Humidity in Lower Limb Prosthesis (Abstract)

G. Coldani, Universit? di Pavia

G. Danese, Universit? di Pavia

R. Gandolfi, Universit? di Pavia

P. Ghidetti, Universit? di Pavia

F. Leporati, Universit? di Pavia

R. Lombardi, Universit? di Pavia

pp. 0368

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A MIMD-Based Multi Threaded Real-Time Processor for Pattern Recognition (Abstract)

F. Lesser, Ruprecht-Karls-University

J. de Cuveland, Ruprecht-Karls-University

V. Lindenstruth, Ruprecht-Karls-University

C. Reichling, Ruprecht-Karls-University

R. Schneider, Ruprecht-Karls-University

M.W. Schulz, Ruprecht-Karls-University

pp. 0372

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Synchronizing a High-Speed SIMD Processor Array (Abstract)

Stefan Lund, Halmstad University

Lars Bengtsson, Chalmers University of Technology

pp. 0376

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Pipelined Genetic Architecture with Fitness on the Fly (Abstract)

A. Ibarra, Universidad Complutense Madrid

J. Lanchares, Universidad Complutense Madrid

J.I. Hidalgo, Universidad Complutense Madrid

F. Saenz, Universidad Complutense Madrid

pp. 0382

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A Wireless Interconnection Network for Parallel Processing (Abstract)

Jacek Marczynski, George Mason University

Daniel Tabak, George Mason University

pp. 0386

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Improving Single-Thread Fetch Performance on a Multithreaded Processor (Abstract)

J.C. Moure, Universidad Aut?noma de Barcelona

R.B. García, Universidad Aut?noma de Barcelona

D.I. Rexachs, Universidad Aut?noma de Barcelona

E. Luque, Universidad Aut?noma de Barcelona

pp. 0390

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An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code (Abstract)

Øyvind Strøm, Atmel Norway

Einar J. Aas, NTNU

pp. 0396

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Adaptability, Extensibility, and Flexibility in Real-Time Operating Systems (Abstract)

Pramote Kuacharoen, Georgia Institute of Technology

Tankut Akgul, Georgia Institute of Technology

Vincent J. Mooney, Georgia Institute of Technology

Vijay K. Madisetti, Georgia Institute of Technology

pp. 0400

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Physical Design-Chair: Agnieszka Konczykowska

Timing Driven Wiring on an Advanced Microprocessor (Abstract)

Paul Kartschoke, IBM Microelectronics Division

Stephen Geissler, IBM Microelectronics Division

pp. 0408

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Interconnect-Driven Short-Circuit Power Modeling (Abstract)

Daniel Eckerbert, Link?pings Universitet

Per Larsson-Edefors, Link?pings Universitet

pp. 0414

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Transistor Chainning with Integrated Dynamic Folding for 1-D Leaf Cell Synthesis (Abstract)

Krzysztof S. Berezowski, Wroclaw University of Technology

pp. 0422

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A Global Routing Technique for Wave-Steering Design Methodology (Abstract)

Nobuo Funabiki, Okayama University

Amit Singh, University of California, Santa Barbara

Arindam Mukherjee, University of California, Santa Barbara

Malgorzata Marek-Sadowska, University of California, Santa Barbara

pp. 0430

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Specialised Architectures-Chair: Daniel Tabak

Synchronizing Low-Cost Energy Aware Sensors in a Short-range Wireless Cell (Abstract)

Mikael M. Nordman, Helsinki University of Technology

Wojciech E. Kozlowski, INFO TECH

Olavi Vähämäki, ABB Corporate Research Oy

pp. 0438

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A Multiple Context Reconfigurable Functional Unit (Abstract)

Michael C. Miller, George Mason University

Daniel Tabak, George Mason University

pp. 0446

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FPGA Based Controller for Heterogeneous Image Processing System (Abstract)

Marek Gorgon, University of Mining and Metallurgy

Jaromir Przybylo, University of Mining and Metallurgy

pp. 0453

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FPGA Implementation of Addition as a Part of the Convolution (Abstract)

Ernest Jamro, AGH Technical University

Kazimierz Wiatr, AGH Technical University

pp. 0458

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Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution (Abstract)

Ernest Jamro, AGH Technical University of Cracow

Kazimierz Wiatr, AGH Technical University of Cracow

pp. 0466

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Author Index (PDF)

pp. 0475