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2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems
On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS
Vancouver, British Columbia Canada
October 03-October 05
ISBN: 978-0-7695-4556-1
| ASCII Text | x | ||
| Nachiket Rajderkar, Marco Ottavi, Salvatore Pontarelli, Jie Han, Fabrizio Lombardi, "On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS," 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 309-315, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011. | |||
| BibTex | x | ||
| @article{ 10.1109/DFT.2011.51, author = {Nachiket Rajderkar and Marco Ottavi and Salvatore Pontarelli and Jie Han and Fabrizio Lombardi}, title = {On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS}, journal ={2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, volume = {0}, year = {2011}, issn = {1550-5774}, pages = {309-315}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2011.51}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) TI - On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS SN - 1550-5774 SP309 EP315 A1 - Nachiket Rajderkar, A1 - Marco Ottavi, A1 - Salvatore Pontarelli, A1 - Jie Han, A1 - Fabrizio Lombardi, PY - 2011 VL - 0 JA - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2011.51
This paper presents a detailed characterization of the effects of intra-gate resistive open defects on nanoscaled CMOS gates as causing faults with timing and pattern sequence dependency. The values of the least detectable resistance are established for different feature sizes using HSPICE. It is found that as the feature size is reduced, the value of the least detectable resistance increases in the presence of a fault resulting in a delay of less than one nanosecond. The use of a low voltage testing technique is investigated for the detection of these faults. Finally, an analytical model that takes into account the gate current is proposed, this model considers the pronounced effect of the gate current at a decreasing feature size, while incurring in a small error compared with simulation results.
Citation:
Nachiket Rajderkar, Marco Ottavi, Salvatore Pontarelli, Jie Han, Fabrizio Lombardi, "On the Effects of Intra-gate Resistive Open Defects in Gates at Nanoscaled CMOS," dft, pp.309-315, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011
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