CSDL - Proceedings D

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

pp. iv

Table of Contents (PDF)

pp. v-ix

Message from the Symposium Chairs (PDF)

pp. x-xi

Organizing Committee (PDF)

pp. xii

Program Committee (PDF)

pp. xiii

In Memoriam: Professor Susumu Horiguchi (PDF)

pp. xiv-xv

TTTC: Test Technology Technical Council (PDF)

pp. xvi-xviii

The Future of Test -- Product Integration and its Impact on Test (Abstract)

Michael Campbell

pp. 3

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Low DPM: Why Do We Need it and What Does it Cost! (Abstract)

Sandeep P. Kumar

pp. 7

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Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems (Abstract)

Jie Qin

pp. 11-19

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Reducing Test Point Area for BIST through Greater Use of Functional Flip-Flops to Drive Control Points (Abstract)

pp. 20-28

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Soft Core Embedded Processor Based Built-In Self-Test of FPGAs (Abstract)

Bradley F. Dutton

Charles E. Stroud

pp. 29-37

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On-chip Generation of the Second Primary Input Vectors of Broadside Tests (Abstract)

Irith Pomeranz

Sudhakar M. Reddy

pp. 38-46

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Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience (Abstract)

Mingjing Chen

Alex Orailoglu

pp. 49-57

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A Novel Hardened Design of a CMOS Memory Cell at 32nm (Abstract)

pp. 58-64

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Novel High Speed Robust Latch (Abstract)

pp. 65-73

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Are Robust Circuits Really Robust? (Abstract)

Sybille Hellebrand

Marc Hunger

pp. 77

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Challenges in Delay Testing of Integrated Circuits (Abstract)

D.M.H. Walker

pp. 81-82

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Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories (Abstract)

Nor Zaidi Haron

Said Hamdioui

pp. 85-93

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Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power (Abstract)

pp. 94-102

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Coded DNA Self-Assembly for Error Detection/Location (Abstract)

Zahra Mashreghian Arani

Masoud Hashempour

Fabrizio Lombardi

pp. 103-111

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Errors in DNA Self-Assembly by Synthesized Tile Sets (Abstract)

pp. 112-120

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Dreams, Plans, and Journey of Reaching Perfect Predictability and Reliability in ASICs (Abstract)

Naveed Sherwani

pp. 123

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Concurrent Detection of Faults Affecting Energy Harvesting Circuits of Self-Powered Wearable Sensors (Abstract)

pp. 127-135

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SNR-Aware Error Detection for Low-Power Discrete Wavelet Lifting Transform in JPEG 2000 (Abstract)

pp. 136-144

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Reduced Precision Checking for a Floating Point Adder (Abstract)

pp. 145-152

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Characterization of Gain Enhanced In-Field Defects in Digital Imagers (Abstract)

pp. 155-163

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Analysis of Resistive Open Defects in a Synchronizer (Abstract)

pp. 164-172

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A Fault Analysis and Classifier Framework for Reliability-Aware SRAM-Based FPGA Systems (Abstract)

pp. 173-181

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On the Functional Qualification of a Platform Model (Abstract)

Giuseppe Di Guglielmo

pp. 182-190

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A Sensor to Detect Normal or Reverse Temperature Dependence in Nanoscale CMOS Circuits (Abstract)

David Wolpert

Paul Ampadu

pp. 193-201

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A Reconfigurable ADC Circuit with Online-Testing Capability and Enhanced Fault Tolerance (Abstract)

Yueran Gao

Haibo Wang

pp. 202-210

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Improving Memory Repair by Selective Row Partitioning (Abstract)

pp. 211-219

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Software-Based Hardware Fault Tolerance for Many-Core Architectures (Abstract)

Hans-Joachim Wunderlich

pp. 223

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Can Functional Test Achieve Low-cost Full Coverage of NoC Faults? (Abstract)

Marcelo Lubaszewski

pp. 224

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Testing of Switch Blocks in Three-Dimensional FPGA (Abstract)

pp. 227-235

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A Study of Side-Channel Effects in Reliability-Enhancing Techniques (Abstract)

Jianwei Dai

Lei Wang

pp. 236-244

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Reliability and Performance Analysis of FPGA-Based Fault Tolerant System (Abstract)

pp. 245-253

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An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs (Abstract)

pp. 254-262

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Minimizing Observation Points for Fault Location (Abstract)

Snehal Udar

Dimitri Kagaris

pp. 263-267

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Optimizing Parametric BIST Using Bio-inspired Computing Algorithms (Abstract)

pp. 268-276

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Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms (Abstract)

pp. 277-285

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System Level Testing via TLM 2.0 Debug Transport Interface (Abstract)

pp. 286-294

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Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments (Abstract)

Nader Alawadhi

Ozgur Sinanoglu

pp. 295-303

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Transient Error Detection and Recovery in Processor Pipelines (Abstract)

Syed Zafar Shazli

Mehdi Baradaran Tahoori

pp. 304-312

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Fault-Tolerant Routing Algorithm for Network on Chip without Virtual Channels (Abstract)

pp. 313-321

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Defect-Tolerant Logic Mapping on Nanoscale Crossbar Architectures and Yield Analysis (Abstract)

Yehua Su

Wenjing Rao

pp. 322-330

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Complementary Formal Approaches for Dependability Analysis (Abstract)

pp. 331-339

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Optimization of Nanoelectronic Systems Reliability Under Massive Defect Density Using Distributed R-fold Modular Redundancy (DRMR) (Abstract)

pp. 340-348

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An ILP formulation to Unify Power Efficiency and Fault Detection at Register-Transfer Level (Abstract)

Yu Liu

Kaijie Wu

pp. 349-357

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Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences (Abstract)

Irith Pomeranz

Sudhakar M. Reddy

pp. 358-366

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Error Control Coding for Multilevel Cell Flash Memories Using Nonbinary Low-Density Parity-Check Codes (Abstract)

Yuu Maeda

Haruhiko Kaneko

pp. 367-375

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Resilience Challenges for Exascale Systems (Abstract)

Norman Paul Jouppi

pp. 379

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Improving the Detectability of Resistive Open Faults in Scan Cells (Abstract)

Fan Yang

Sreejit Chakravarty

Narendra Devta-Prasanna

Sudhakar M. Reddy

Irith Pomeranz

pp. 383-391

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An Incremental Approach to Functional Diagnosis (Abstract)

pp. 392-400

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Generating Diverse Test Sets for Multiple Fault Detections Based on Fault Cone Partitioning (Abstract)

pp. 401-409

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Thermal Driven Test Access Routing in Hyper-interconnected Three-Dimensional System-on-Chip (Abstract)

Unni Chandran

Dan Zhao

pp. 410-418

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Workload-Cognizant Impact Analysis and its Applications in Error Detection and Tolerance in Modern Microprocessors (Abstract)

Yiorgos Makris

pp. 421

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A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS (Abstract)

Adit D. Singh

pp. 422

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Error Correction Codes for SEU and SEFI Tolerant Memory Systems (Abstract)

M. Re

pp. 425-430

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Dual-Layer Cooperative Error Control for Reliable Nanoscale Networks-on-Chip (Abstract)

Qiaoyan Yu

Paul Ampadu

pp. 431-439

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Burst Error Detection Hybrid ARQ with Crosstalk-Delay Reduction for Reliable On-chip Interconnects (Abstract)

Bo Fu

Paul Ampadu

pp. 440-448

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Data Learning Techniques for Functional/System Fmax Prediction (Abstract)

Li-C. Wang

pp. 451

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Author Index (PDF)

pp. 453-455

Roster Page (PDF)

pp. 456