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2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
System Level Testing via TLM 2.0 Debug Transport Interface
Chicago, Illinois
October 07-October 09
ISBN: 978-0-7695-3839-6
| ASCII Text | x | ||
| Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto, Alessandro Savino, "System Level Testing via TLM 2.0 Debug Transport Interface," 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 286-294, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/DFT.2009.46, author = {Stefano Di Carlo and Nadereh Hatami and Paolo Prinetto and Alessandro Savino}, title = {System Level Testing via TLM 2.0 Debug Transport Interface}, journal ={2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, volume = {0}, year = {2009}, issn = {1550-5774}, pages = {286-294}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2009.46}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) TI - System Level Testing via TLM 2.0 Debug Transport Interface SN - 1550-5774 SP286 EP294 A1 - Stefano Di Carlo, A1 - Nadereh Hatami, A1 - Paolo Prinetto, A1 - Alessandro Savino, PY - 2009 KW - TLM KW - transaction level modeling KW - system level testing KW - TLM 2.0 VL - 0 JA - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2009.46
With the rapid increase in the complexity of digital circuits, the design abstraction level has to grow to face the new needs of system designers in the early phases of the design process. Along with this evolution, testing and test facilities should be improved in the early stages of the design to provide the architecture with functional test facilities to be later synthesized testing infrastructures according to designer’s requirements. These test infrastructures could be translated, into testing facilities at lower levels of abstraction, from which automatic synthesis tools are available. Starting from the increasing use of TLM in hardware design industry, the paper aims at providing a mechanism to fill the gap between the design abstraction level and the level in which testing methodologies are applied. To do the job, the TLM 2.0 “debug transport interface” is used and methods are introduced to synthesize it into known test access methods at RTL.
Index Terms:
TLM, transaction level modeling, system level testing, TLM 2.0
Citation:
Stefano Di Carlo, Nadereh Hatami, Paolo Prinetto, Alessandro Savino, "System Level Testing via TLM 2.0 Debug Transport Interface," dft, pp.286-294, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
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