|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
 Digg  Furl  Spurl  Blink  Simpy  Google  Del.icio.us  Y!MyWeb | ||
| Search | ||
| ||
2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power
Chicago, Illinois
October 07-October 09
ISBN: 978-0-7695-3839-6
| ASCII Text | x | ||
| Aaron Dingler, M. Jafar Siddiq, Michael Niemier, X. Sharon Hu, M. Tanvir Alam, Gary Bernstein, Wolfgang Porod, "Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power," 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 94-102, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/DFT.2009.44, author = {Aaron Dingler and M. Jafar Siddiq and Michael Niemier and X. Sharon Hu and M. Tanvir Alam and Gary Bernstein and Wolfgang Porod}, title = {Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power}, journal ={2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, volume = {0}, year = {2009}, issn = {1550-5774}, pages = {94-102}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2009.44}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) TI - Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power SN - 1550-5774 SP94 EP102 A1 - Aaron Dingler, A1 - M. Jafar Siddiq, A1 - Michael Niemier, A1 - X. Sharon Hu, A1 - M. Tanvir Alam, A1 - Gary Bernstein, A1 - Wolfgang Porod, PY - 2009 KW - magnetic logic KW - MQCA KW - magnetic yoke KW - fabrication variation KW - low power KW - clocking VL - 0 JA - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2009.44
Circuits based on magnetic logic have shown great promise as an extremely low power alternative to CMOS based circuits. However, the success or failure of such circuits hinges on the existence of a locally controllable and low power clock field. Existing work has largely assumed the availability of such a clock field that would be almost impossible to fabricate or that exhibits an ideal distribution in space. This paper uses a fabricatable clock structure proposed in [10] as the basis to investigate all possible non-ideal properties (due to fabrication limitations and variations) of the resulting clock field. How such a clock impacts the logical correctness of a magnetic circuit element is verified via micromagnetic simulation. The impact on performance and power is also considered.
Index Terms:
magnetic logic, MQCA, magnetic yoke, fabrication variation, low power, clocking
Citation:
Aaron Dingler, M. Jafar Siddiq, Michael Niemier, X. Sharon Hu, M. Tanvir Alam, Gary Bernstein, Wolfgang Porod, "Controlling Magnetic Circuits: How Clock Structure Implementation will Impact Logical Correctness and Power," dft, pp.94-102, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
Usage of this product signifies your acceptance of the Terms of Use.