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2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
A Novel Hardened Design of a CMOS Memory Cell at 32nm
Chicago, Illinois
October 07-October 09
ISBN: 978-0-7695-3839-6
| ASCII Text | x | ||
| Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi, "A Novel Hardened Design of a CMOS Memory Cell at 32nm," 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 58-64, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009. | |||
| BibTex | x | ||
| @article{ 10.1109/DFT.2009.18, author = {Sheng Lin and Yong-Bin Kim and Fabrizio Lombardi}, title = {A Novel Hardened Design of a CMOS Memory Cell at 32nm}, journal ={2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, volume = {0}, year = {2009}, issn = {1550-5774}, pages = {58-64}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFT.2009.18}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) TI - A Novel Hardened Design of a CMOS Memory Cell at 32nm SN - 1550-5774 SP58 EP64 A1 - Sheng Lin, A1 - Yong-Bin Kim, A1 - Fabrizio Lombardi, PY - 2009 KW - hardening KW - soft error tolerance KW - memory KW - nano CMOS VL - 0 JA - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ER - | |||
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/DFT.2009.18
This paper proposes a new design for hardening a CMOS memory cell at the nano feature size of 32nm. By separating the circuitry for the write and read operations, the static stability of the proposed cell configuration increases more than 4.4 times at typical process corner, respectively compared to previous designs. Simulation shows that by appropriately sizing the pull-down transistors, the proposed cell results in a 40% higher critical charge and 13% less delay than the conventional design. Simulation results are provided using the predictive technology file for 32nm feature size in CMOS to show that the proposed hardened memory cell is best suited when designing memories for both high performance and soft error tolerance.
Index Terms:
hardening, soft error tolerance, memory, nano CMOS
Citation:
Sheng Lin, Yong-Bin Kim, Fabrizio Lombardi, "A Novel Hardened Design of a CMOS Memory Cell at 32nm," dft, pp.58-64, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
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