CSDL - Proceedings D

20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Copyright (PDF)

pp. iv

Introduction

Message from the Symposium Chairs (PDF)

pp. x-xi

Committees (PDF)

pp. xii

Yield Analysis and Modeling

Defects, Yield, and Design in Sublithographic Nano-electronics (Abstract)

Mehdi B. Tahoori, Northeastern University, Boston, MA

pp. 3-11

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An ILP Formulation for Yield-driven Architectural Synthesis (Abstract)

Zhaojun Wo, University of Massachusetts

Israel Koren, University of Massachusetts

Maciej Ciesielski, University of Massachusetts

pp. 12-20

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Design and Analysis of Self-Repairable MEMS Accelerometer (Abstract)

Xingguo Xiong, Chinese University of Hong Kong

Yu-Liang Wu, Chinese University of Hong Kong

Wen-Ben Jone, Chinese University of Hong Kong

pp. 21-32

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Scan Design and Test Data Compression

Low Power BIST Based on Scan Partitioning (Abstract)

Jinkyu Lee, University of Texas, Austin

Nur A. Touba, University of Texas, Austin

pp. 33-41

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Using Statistical Transformations to Improve Compression for Linear Decompressors (Abstract)

Samuel I. Ward, IBM Systems andTechnology Group

Chris Schattauer, University of Texas, Austin

Nur A. Touba, University of Texas, Austin

pp. 42-50

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Securing Scan Design Using Lock and Key Technique (Abstract)

Jeremy Lee, University of Maryland Baltimore County

Mohammed Tehranipoor, University of Maryland Baltimore County

Chintan Patel, University of Maryland Baltimore County

Jim Plusquellic, University of Maryland Baltimore County

pp. 51-62

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Reconfiguration

A Genetic Approach for the Reconfiguration of Degradable Processor Arrays (Abstract)

Masaru Fukushi, Tohoku University

Yusuke Fukushima, Tohoku University

Susumu Horiguchi, Tohoku University

pp. 63-71

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Incorporating Error Detection and Online Reconfiguration into a Regular Architecture for the Advanced Encryption Standard (Abstract)

L. Breveglieri, Politecnico di Milano, Milano, ITALY

I. Koren, University of Massachusetts, Amherst

P. Maistri, Politecnico di Milano, Milano, ITALY

pp. 72-80

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An Integrated ECC and Redundancy Repair Scheme for Memory Reliability Enhancement (Abstract)

Chin-Lung Su, National Tsing Hua University

Yi-Ting Yeh, National Tsing Hua University

Cheng-Wen Wu, National Tsing Hua University

pp. 81-92

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Error Correcting Codes and Circuits

Error Control Coding for Semiconductor Memory Systems in the Space Radiation Environment (Abstract)

Haruhiko Kaneko, Japan Aerospace Exploration Agency

pp. 93-101

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Concurrent Error Detection of Polynomial Basis Multiplication over Extension Fields using a Multiple-bit Parity Scheme (Abstract)

S. Bayat-Sarmadi, University of Waterloo, ON, Canada

M. A. Hasan, University of Waterloo, ON, Canada

pp. 102-110

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A Self Checking Reed Solomon Encoder: Design and Analysis (Abstract)

G.C. Cardarilli, University of Rome

S. Pontarelli, University of Rome

M. Re, University of Rome

A. Salsano, University of Rome

pp. 111-119

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Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes (Abstract)

Jien-Chung Lo, University of Rhode Island

Yu-Lun Wan, University of Rhode Island

Eiji Fujiwara, Tokyo Institute of Technology

pp. 120-130

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Fault Detection and Tolerance for Sensor and Flash Memory

Flash Memory Cell: Parametric Test Data Reconstruction for Process Monitoring (Abstract)

B. Saillet, IMT - Technop?le de Ch?teau Gombert

J.M. Portal, IMT - Technop?le de Ch?teau Gombert

D. N?, ST-Microelectronics ZI de Rousset BP 2

pp. 131-139

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Noise Analysis of Fault Tolerant Active Pixel Sensors (Abstract)

Cory Jung, Simon Fraser University,

Mohammad H. Izadi, Simon Fraser University

Michelle L. La Haye, Simon Fraser University

pp. 140-148

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On-Line Identification of Faults in Fault-Tolerant Imagers (Abstract)

Glenn H. Chapman, Simon Fraser University

Israel Koren, University of Massachusetts, Amherst

Zahava Koren, University of Massachusetts, Amherst

Jozsef Dudas, Simon Fraser University

Cory Jung, Simon Fraser University

pp. 149-157

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Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems (Abstract)

Glenn H. Chapman, Simon Fraser University

Vijay Jain, University of South Florida, Tampa

Shekhar Bhansal, University of South Florida, Tampa

pp. 158-168

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Invited Talks

Error Tolerance, Let's Think Out of the Box

Error Tolerance in Razor Processor

Delay Fault Test and Timing Consideration

The Other Side of the Timing Equation: a Result of Clock Faults (Abstract)

C. Metra, DEIS Univ. of Bologna

M. Oma?, DEIS Univ. of Bologna

D. Rossi, DEIS Univ. of Bologna

J. M. Cazeaux, DEIS Univ. of Bologna

TM Mak, DEIS Univ. of Bologna

pp. 169-177

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A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits (Abstract)

Lei Wu, Texas A&M University

D. M. H. Walker, Texas A&M University

pp. 178-186

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Improving Transition Delay Fault Coverage Using Hybrid Scan-Based Technique (Abstract)

Nisar Ahmed, ASIC Product Development Center, Texas Instruments India

Mohammad Tehranipoor, Univ. of Maryland Baltimore

pp. 187-198

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Defect and Fault Tolerant Design in QCA Circuits

Defect Characterization and Tolerance of QCA Sequential Devices and Circuits (Abstract)

M. Momenzadeh, Northeastern University

J. Huang, Northeastern University

F. Lombardi, Northeastern University

pp. 199-207

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Modeling QCA Defects at Molecular-level in Combinational Circuits (Abstract)

Mariam Momenzadeh, Northeastern University, Boston

Marco Ottavi, Northeastern University, Boston

Fabrizio Lombardi, Northeastern University, Boston

pp. 208-216

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QCA-Based Majority Gate Design under Radius of Effect-Induced Faults (Abstract)

Zachary D. Patitz, Oklahoma State University

Nohpill Park, Oklahoma State University

Minsu Choi, University of Missouri-Rolla

Fred J. Meyer, Wichita State University, Kansas

pp. 217-228

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A Novel Pulse Echo Correlation Tool for Transmission Path Testing and Fault Finding using Pseudorandom Binary Sequences (Abstract)

Interconnect Test

David M. Horan, Cork Institute of Technology, Cork, IRELAND

Richard A. Guinee, Cork Institute of Technology, Cork, IRELAND

pp. 229-237

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Methodologies and Algorithms for Testing Switch-Based NoC Interconnects (Abstract)

Cristian Grecu, University of British Columbia

Partha Pande, University of British Columbia

Baosheng Wang, University of British Columbia

Andr? Ivanov, University of British Columbia

Res Saleh, University of British Columbia

pp. 238-246

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Test of Interconnection Opens Considering Coupling Signals (Abstract)

Roberto Gomez, National Institute for Astrophysics, Optics and Electronics - INAOE

Alejandro Giron, National Institute for Astrophysics, Optics and Electronics - INAOE

Victor Champac, National Institute for Astrophysics, Optics and Electronics - INAOE

pp. 247-258

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Case Studies and Applications

FPGA oriented design of parity sharing RS codecs (Abstract)

G.C. Cardarilli, University of Rome

S. Pontarelli, University of Rome

M. Re, University of Rome

A. Salsano, University of Rome

pp. 259-265

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A Software-Based Concurrent Error Detection Technique for PowerPC Processor-based Embedded Systems (Abstract)

Mahdi Fazeli, Sharif University of Technology

Reza Farivar, Sharif University of Technology

Seyed Ghassem Miremadi, Sharif University of Technology

pp. 266-274

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Soft Errors induced by single heavy ions in Floating Gate memory arrays (Abstract)

G. Cellere, Padova University

A. Paccagnella, Padova University

A. Visconti, STMicroelectronics Central R&D

M. Bonanomi, STMicroelectronics Central R&D

pp. 275-284

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On the Modeling and Analysis of Jitter in ATE Using Matlab (Abstract)

Kyung Ki Kim, Northeastern University, Boston

Jing Huang, Northeastern University, Boston

Yong-Bin Kim, Northeastern University, Boston

Fabrizio Lombardi, Northeastern University, Boston

pp. 285-293

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Data Dependent Jitter (DDJ) Characterization Methodology (Abstract)

Kyung Ki Kim, Northeastern University, Boston

Yong-Bin Kim, Northeastern University, Boston

Fabrizio Lombardi, Northeastern University, Boston

pp. 294-304

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Interactive Session

Defect Tolerance for Molecular Electronics-Based NanoFabrics Using Built-In Self-Test Procedure (Abstract)

Mohammad Tehranipoor, University of Maryland, Baltimore

pp. 305-313

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Reliable Digital Circuits Design using Sigma-Delta Modulated Signals (Abstract)

Erik Schuler, Universidade Federal do Rio Grande do Sul

Luigi Carro, Universidade Federal do Rio Grande do Sul

pp. 314-324

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A Technique for Modular Design of Self-Checking Carry-Select Adder (Abstract)

D. P. Vasudevan, University of Arkansas, Fayetteville

P. K. Lala, University of Arkansas, Fayetteville

pp. 325-333

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A model of soft error e.ects in generic IP processors (Abstract)

C. Bolchini, Politecnico di Milano

A. Miele, Politecnico di Milano

F. Salice, Politecnico di Milano

D. Sciuto, Politecnico di Milano

pp. 334-342

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Implementation of Concurrent Checking Circuits by Independent Sub-circuits (Abstract)

Vladimir Ostrovsky, Bar-Ilan University, Ramat Gan

Ilya Levin, Bar-Ilan University, Ramat Gan

pp. 343-351

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Multiple Transient Faults in Logic: An Issue for Next Generation ICs (Abstract)

Daniele Rossi, DEIS, University of Bologna

Martin Oma?, DEIS, University of Bologna

Fabio Toma, DEIS, University of Bologna

Cecilia Metra, DEIS, University of Bologna

pp. 352-360

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Efficient Exact Spare Allocation via Boolean Satisfiability (Abstract)

Fang Yu, Institute of Information Science, Academia Sinica

Chung-Hung Tsai, Institute of Information Science, Academia Sinica

Yao-Wen Huang, Institute of Information Science, Academia Sinica

D. T. Lee, Institute of Information Science, Academia Sinica

Hung-Yau Lin, National Taiwan University

Sy-Yen Kuo, National Taiwan University

pp. 361-370

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On the Effect of Stuck-at Faults on Delay-insensitive Nanoscale Circuits (Abstract)

J. Di, University of Arkansas

P.K. Lala, University of Arkansas

D. Vasudevan, University of Arkansas

pp. 371-379

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Delay Test Generation with All Reachable Output Propagation and Multiple Excitations (Abstract)

Bhushan Vaidya, Northeastern University, Boston, MA

Mehdi B. Tahoori, Northeastern University, Boston, MA

pp. 380-388

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Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment (Abstract)

Pedram A. Riahi, Northeastern University

Zainalabedin Navabi, Northeastern University

Fabrizio Lombardi, Northeastern University

pp. 389-397

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On Generating Pseudo-Functional Delay Fault Tests for Scan Designs (Abstract)

Zhuo Zhang, University of Iowa

Sudhakar M. Reddy, University of Iowa

Irith Pomeranz, Purdue University

pp. 398-405

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Should Illinois-Scan Based Architectures be Centralized or Distributed? (Abstract)

Ahmad Al-Yamani, KFUPM, Dhahran, Saudi Arabia

Narendra Devta-Prasanna, Univ. of Iowa, Iowa

Arun Gunda, LSI Logic Corp.

pp. 406-414

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On Generating Tests to Cover Diverse Worst-Case Timing Corners (Abstract)

Leonard Lee, ECE, UC-Santa Barbara

Sean Wu, ECE, UC-Santa Barbara

Charles H-P Wen, ECE, UC-Santa Barbara

Li-C. Wang, ECE, UC-Santa Barbara

pp. 415-426

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Approaches for Soft Error

Computing Cache Vulnerability to Transient Errors and Its Implication (Abstract)

Wei Zhang, ECE, Southern Illinois Univ. Carbondale

pp. 427-435

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A design flow for protecting FPGA-based systems against single event upsets (Abstract)

L. Sterpone, Politecnico di Torino

M. Violante, Politecnico di Torino

pp. 436-444

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An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors (Abstract)

P. Bernardi, Politecnico di Torino

L. Bolzani, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

M. Violante, Politecnico di Torino

pp. 445-453

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A Low Power Soft Error Suppression Technique for Dynamic Logic (Abstract)

Jeetendra Kumar, Analog Devices Inc.

Mehdi B. Tahoori, Northeastern University

pp. 454-462

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Soft Error Modeling and Protection for Sequential Elements (Abstract)

Hossein Asadi, Northeastern University

Mehdi B. Tahoori, Northeastern University

pp. 463-474

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On-line and Concurrent Fault Detection

Recovery During Concurrent On-Line Testing of Identical Circuits (Abstract)

Irith Pomeranz, Purdue University

Sudhakar M. Reddy, University of Iowa

pp. 475-483

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Efficient Failure Detection in Pipelined Asynchronous Circuits (Abstract)

Song Peng, Cornell University

Rajit Manohar, Cornell University

pp. 484-493

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On the Transformation of Manufacturing Test Sets into On-Line Test Sets for Microprocessors (Abstract)

E. S?nchez, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

G. Squillero, Politecnico di Torino

pp. 494-504

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Fault and Error Tolerant Systems

Fault-Tolerant Wormhole Switching with Backtracking Capability (Abstract)

Masato Kitakami, Chiba University

Manabu Sueishi, Chiba University

pp. 505-513

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Analysis and Testing for Error Tolerant Motion Estimation (Abstract)

Hyukjune Chung, University of Southern California

Antonio Ortega, University of Southern California

pp. 514-522

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Hardware Testing For Error Tolerant Multimedia Compression based on Linear Transforms (Abstract)

In Suk Chong, University of Southern California

Antonio Ortega, University of Southern California

pp. 523-534

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Test Scheduling and Software-based Test

Software-Based Self-Test for Pipelined Processors: A Case Study (Abstract)

M. Hatzimihail, University of Piraeus, Greece

M. Psarakis, University of Piraeus, Greece

G. Xenoulis, University of Piraeus, Greece

D. Gizopoulos, University of Piraeus, Greece

A. Paschalis, University of Athens, Greece

pp. 535-543

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Improving Thermal-Safe Test Scheduling for Core-Based Systems-on-Chip Using Shift Frequency Scaling (Abstract)

Enkelejda Tafaj, University of Southampton

Paul Rosinger, University of Southampton

Bashir M. Al-Hashimi, University of Southampton

Krishnendu Chakrabarty, Duke University

pp. 544-551

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Thermal-Aware Test Scheduling and Hot Spot Temperature Minimization for Core-Based Systems (Abstract)

Chunsheng Liu, University of Nebraska-Lincoln

Kugesh Veeraraghavant, University of Nebraska-Lincoln

Vikram Iyengar, IBM Microelectronics

pp. 552-562

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Testing and Design for Analog Circuits

Design of a CMOS Operational Amplifier Amenable to Extreme Voltage Stress (Abstract)

Shaolei Quan, Michigan State University, USA

Meng-Yao Liu, Natinal Central University, Taiwan

Chin-Long Wey, Natinal Central University, Taiwan

pp. 563-572

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Characteristics of Fault Diagnosis for Analog Circuits Based on Preset Test (Abstract)

Yukiya Miura, Tokyo Metropolitan University

pp. 573-581

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A New Test Methodology For DNL Error In Flash ADC?s (Abstract)

Michael Wieckowski, University of Rochester

John Liobe, University of Rochester

Quentin Diduck, University of Rochester

Martin Margala, University of Rochester

pp. 582-590

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A High Frequency, Low Jitter Auto-Calibration Phase-Locked Loop with Built-in-Self-Test (Abstract)

Sadeka Ali, University of Rochester

Gregory J. Briggs, University of Rochester

Martin Margala, University of Rochester

pp. 591-600

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Author Index

Author Index (Abstract)

pp. 601

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