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19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'04)
Cannes, France
October 10-October 13
ISBN: 0-7695-2241-6
Table of Contents
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Committees (PDF)
pp. xii-xii
Session 1: Yield and Defects I
Roman Barsky, Technion, Haifa, Israel
Israel A. Wagner, IBM Haifa Labs, Israel
pp. 2-10
X. Wang, IBM Corp, Essex Junction (VT) USA
M. Ottavi, Northeastern University Boston (MA) USA
F. Meyer, Wichita State University Wichita (KS) USA
F. Lombardi, Northeastern University Boston (MA) USA
pp. 11-19
Yu-Tsao Hsing, National Tsing Hua University, Hsinchu, Taiwan
Chih-Wea Wang, National Tsing Hua University, Hsinchu, Taiwan
Ching-Wei Wu, National Tsing Hua University, Hsinchu, Taiwan
Chih-Tsun Huang, National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu, National Tsing Hua University, Hsinchu, Taiwan
pp. 20-28
Session 2: Yield and Defects II
Jing Huang, Northeastern University, Boston, MA
Mariam Momenzadeh, Northeastern University, Boston, MA
Mehdi B. Tahoori, Northeastern University, Boston, MA
Fabrizio Lombardi, Northeastern University, Boston, MA
pp. 30-38
Alexandre Schmid, Swiss Federal Institute of Technology EPFL, Switzerland
Yusuf Leblebici, Swiss Federal Institute of Technology EPFL, Switzerland
pp. 39-47
Shanrui Zhang, University of Missouri-Rolla
Minsu Choi, University of Missouri-Rolla
Nohpill Park, Oklahoma State University, Stillwater
Fabrizio Lombardi, Northeastern University, Boston
pp. 48-56
Session 3: Optoelectronics
Michelle L. La Haye, Simon Fraser University, Canada
Glenn H. Chapman, Simon Fraser University, Canada
Cory Jung, Simon Fraser University, Canada
Desmond Y. H. Cheung, Simon Fraser University, Canada
Sunjaya Djaja, Simon Fraser University, Canada
Benjamin Wang, Simon Fraser University, Canada
Gary Liaw, Simon Fraser University, Canada
Yves Audet, ?cole Polytechnique, Canada
pp. 58-66
Glenn H. Chapman, Simon Fraser University, Canada
Vijay Jain, University of South Florida, Tampa, Florida
pp. 67-75
Session 4: Defect and Fault Tolerance
Ammar Aljer, University of Sciences and Technologies of Lille 1
Philippe Devienne, University of Sciences and Technologies of Lille 1
pp. 78-86
Mohamed Abbas, University of Tokyo, Japan
Makoto Ikeda, University of Tokyo, Japan
Kunihiro Asada, University of Tokyo, Japan
pp. 87-95
Jing Huang, Northeastern University, Boston, MA
Mehdi B. Tahoori, Northeastern University, Boston, MA
Fabrizio Lombardi, Northeastern University, Boston, MA
pp. 96-104
Session 5: Memory Test
S. Bertazzoni, University of Rome "Tor Vergata", Italy
D. Di Giovenale, University of Rome "Tor Vergata", Italy
M. Salmeri, University of Rome "Tor Vergata", Italy
A. Mencattini, University of Rome "Tor Vergata", Italy
A. Salsano, University of Rome "Tor Vergata", Italy
M. Florean, University of Rome "Tor Vergata", Italy
J. Wyss, INFN Sezione di Pisa, Italy
R. Rando, INFN Sezione di Padova, Italy
S. Lora, Istituto per la Sintesi Organica e la Fotoreattivit?, Italy
pp. 106-110
X. Wang, IBM Corp, Essex Junction (VT) USA
M. Ottavi, Northeastern University Boston (MA) USA
F. Lombardi, Northeastern University Boston (MA) USA
pp. 111-119
Baosheng Wang, University of British Columbia, Vancouver, Canada
Yuejian Wu, Nortel Networks, Ontario, Canada
Andr? Ivanov, University of British Columbia, Vancouver, Canada
pp. 120-128
Session 6: Diagnosis
Guido Bertoni, STMicroelectronics, Milano, Italy
Luca Breveglieri, Politecnico di Milano, Italy
Israel Koren, University of Massachusetts, Amherst
Paolo Maistri, Politecnico di Milano, Italy
pp. 130-138
Shi-Yu Huang, National Tsing-Hua University, Taiwan
pp. 139-147
Session 7: Error Correcting Codes
H. Hashempour, Northeastern University, Boston, Mass
F. Lombardi, Northeastern University, Boston, Mass
pp. 150-157
G. C. Cardarilli, University of Rome "Tor Vergata", Italy
M. Ottavi, University of Rome "Tor Vergata", Italy
S. Pontarelli, University of Rome "Tor Vergata", Italy
M. Re, University of Rome "Tor Vergata", Italy
A. Salsano, University of Rome "Tor Vergata", Italy
pp. 158-164
Ping-Hsun Hsieh, National Taiwan University, Taipei
Ing-Yi Chen, National Taipei University of Technology, Taiwan
Yu-Ting Lin, National Taiwan University, Taipei
Sy-Yen Kuo, National Taiwan University, Taipei
pp. 165-172
Session 8: Interconnect Faults
Ajoy K. Palit, University of Bremen, Germany
V. Meyer, University of Bremen, Germany
W. Anheier, University of Bremen, Germany
Juergen Schloeffel, Philips Semiconductors, Germany
pp. 174-182
M. Favalli, DI - University of Ferrara, Italy
pp. 191-199
Session 9: RF and High Speed Circuits
Martin Oma?, D.E.I.S. University of Bologna, Italy
Daniele Rossi, D.E.I.S. University of Bologna, Italy
Cecilia Metra, D.E.I.S. University of Bologna, Italy
pp. 202-210
Tejasvi Das, Rochester Institute of Technology
Anand Gopalan, Rochester Institute of Technology
Clyde Washburn, Rochester Institute of Technology
P. R. Mukund, Rochester Institute of Technology
pp. 211-219
Jerzy Dabrowski, Link?ping University, Sweden
Javier Gonzalez Bayon, Link?ping University, Sweden
pp. 220-228
Session 10: Analog Testing
Ad?o A. de Souza Jr., Instituto de Inform?tica -UFRGS. Porto Alegre, Brazil
Luigi Carro, Instituto de Inform?tica -UFRGS. Porto Alegre, Brazil
pp. 239-247
Session 11: Interactive Session
L. Anghel, TIMA Laboratory, Grenoble, France
E. Sanchez, Politecnico di Torino, Italy
M. Sonza Reorda, Politecnico di Torino, Italy
G. Squillero, Politecnico di Torino, Italy
R. Velazco, TIMA Laboratory, Grenoble, France
pp. 250-255
Najwa Aaraj, American University of Beirut, Lebanon
Anis Nazer, American University of Beirut, Lebanon
Ali Chehab, American University of Beirut, Lebanon
Ayman Kayssi, American University of Beirut, Lebanon
pp. 264-271
Brian Peng, National Taiwan University
Ing-Yi Chen, National Taipei University of Technology
Sy-Yen Kuo, National Taiwan University
Colin Bolger, VIA Technology Incorporation, Taiwan
pp. 272-279
Yinhe Han, Chinese Academy of Sciences, Beijing, China
Yu Hu, Chinese Academy of Sciences, Beijing, China
Huawei Li, Chinese Academy of Sciences, Beijing, China
Xiaowei Li, Chinese Academy of Sciences, Beijing, China
Anshuman Chandra, Synopsys, Inc., Mountain View, CA
pp. 298-305
Hung-Yau Lin, National Taiwan University, Taipei
Fu-Min Yeh, Chung-Shan Institute of Science and Technology, Taoyuan, Taiwan
Ing-Yi Chen, University of Technology, Taipei, Taiwan
Sy-Yen Kuo, National Taiwan University, Taipei
pp. 306-313
S. Bhunia, Purdue University, IN
H. Mahmoodi, Purdue University, IN
A. Raychowdhury, Purdue University, IN
K. Roy, Purdue University, IN
pp. 314-315
H. Hashempour, Northeastern University, Boston, MA
L. Schiano, Northeastern University, Boston, MA
F. Lombardi, Northeastern University, Boston, MA
pp. 316-323
D. P. Vasudevan, University of Arkansas, Fayetteville
P. K. Lala, University of Arkansas, Fayetteville
J. P. Parkerson, University of Arkansas, Fayetteville
pp. 324-331
Nitin Parimi, University of Alberta, Canada
Xiaoling Sun, University of Alberta, Canada
pp. 332-338
John Y. Fong, Texas Instruments, Dallas, TX
Randy Acklin, Texas Instruments, Dallas, TX
John Roscher, Texas Instruments, Dallas, TX
Feng Li, Agilent Technologies, Santa Clara, CA
Cindy Laird, Agilent Technologies, Santa Clara, CA
Cezary Pietrzyk, Agilent Technologies, Santa Clara, CA
pp. 347-355
Shanrui Zhang, University of Missouri-Rolla
Minsu Choi, University of Missouri-Rolla
Nohpill Park, Oklahoma State University, Stillwater
pp. 356-364
Session 12: Error Detection and Correction
M. Favalli, DI - University of Ferrara, Italy
pp. 366-376
Wayne Burleson, University of Massachusetts, Amherst
Israel Koren, University of Massachusetts, Amherst
Atul Maheshwari, University of Massachusetts, Amherst
pp. 377-385
Nicola Bombieri, Universit? di Verona
Franco Fummi, Universit? di Verona
Graziano Pravadelli, Universit? di Verona
pp. 386-394
Yung-Yuan Chen, Chung-Hua University, Hsin-Chu, Taiwan
Kun-Feng Chen, Chung-Hua University, Hsin-Chu, Taiwan
pp. 395-402
Session 13: System-on-Chip Test
P. Bernardi, Politecnico di Torino, Italy
M. Rebaudengo, Politecnico di Torino, Italy
M. Sonza Reorda, Politecnico di Torino, Italy
pp. 404-412
Gang Zeng, Chiba University, Japan
Hideo Ito, Chiba University, Japan
pp. 413-421
Session 14: Circuit and System Reliability and Dependability
M. Sonza Reorda, Politecnico di Torino, Italy
M. Violante, Politecnico di Torino, Italy
pp. 424-432
C. Bolchini, Politecnico di Milano
A. Miele, Politecnico di Milano
F. Salice, Politecnico di Milano
D. Sciuto, Politecnico di Milano
L. Pomante, CEFRIEL, Milano, Italy
pp. 433-441
T. Feng, Oklahoma State University, Stillwater
N. Park, Oklahoma State University, Stillwater
Y. Kim, Northeastern University, Boston, MA
F. Lombardi, Northeastern University, Boston, MA
F. J. Meyer, Wichita State University, KS
pp. 442-450
R. Leveugle, TIMA Laboratory, France
D. Cimonnet, TIMA Laboratory, France
A. Ammari, TIMA Laboratory, France
pp. 451-458
Session 15: Novel Test Approaches
Jennifer Dworak, Texas A&M University, College Station, Texas
James Wingfield, Texas A&M University, College Station, Texas
M. Ray Mercer, Texas A&M University, College Station, Texas
pp. 460-468
Session 16: FPGA and Reconfigurable Circuits
Yen-Lin Peng, National Tsing Hua University, Hsinchu, Taiwan
Jing-Jia Liou, National Tsing Hua University, Hsinchu, Taiwan
Chih-Tsun Huang, National Tsing Hua University, Hsinchu, Taiwan
Cheng-Wen Wu, National Tsing Hua University, Hsinchu, Taiwan
pp. 478-486
Author Index (PDF)
pp. 505-506
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