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18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Error Correcting Codes for Crosstalk Effect Minimization
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
| ASCII Text | x | ||
| D. Rossi, S. Cavallotti, C. Metra, "Error Correcting Codes for Crosstalk Effect Minimization," 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 257, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003. | |||
| BibTex | x | ||
| @article{ 10.1109/DFTVS.2003.1250120, author = {D. Rossi and S. Cavallotti and C. Metra}, title = {Error Correcting Codes for Crosstalk Effect Minimization}, journal ={2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, volume = {0}, year = {2003}, issn = {1063-6722}, pages = {257}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250120}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) TI - Error Correcting Codes for Crosstalk Effect Minimization SN - 1063-6722 SP EP A1 - D. Rossi, A1 - S. Cavallotti, A1 - C. Metra, PY - 2003 KW - null VL - 0 JA - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ER - | |||
In this paper we present an analysis of crosstalk effects on busses implementing error correcting codes. We show that the redundancy introduced by these codes can be exploited in order to avoid the worst case crosstalk-induced delay. Our analysis is based on the evaluation of the coupling effective capacitance which need to be charged during bus activity. In particular, we analyze the cases of the Hamming and Dual Rail codes. We show that Hamming codes do not allow us to avoid the most delay costly bus transitions, while this can be the case for Dual Rail codes. Furthermore, we illustrate that, by increasing the redundancy of the Dual Rail code by only one bit, even higher crosstalk-induced delay reductions can be achieved. Finally, we show that a further improvement can be obtained by an optimized placing of the bus wires.
Citation:
D. Rossi, S. Cavallotti, C. Metra, "Error Correcting Codes for Crosstalk Effect Minimization," dft, pp.257, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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