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18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03)
Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits
Boston, Massachusetts
November 03-November 05
ISBN: 0-7695-2042-1
| ASCII Text | x | ||
| Marco S. Dragic, Martin Margala, "Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits," 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp. 124, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003. | |||
| BibTex | x | ||
| @article{ 10.1109/DFTVS.2003.1250103, author = {Marco S. Dragic and Martin Margala}, title = {Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits}, journal ={2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)}, volume = {0}, year = {2003}, issn = {1063-6722}, pages = {124}, doi = {http://doi.ieeecomputersociety.org/10.1109/DFTVS.2003.1250103}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - CONF JO - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) TI - Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits SN - 1063-6722 SP EP A1 - Marco S. Dragic, A1 - Martin Margala, PY - 2003 KW - null VL - 0 JA - 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ER - | |||
A feasibility of non-specification based method for testing of analog integrated circuits in 0.13?m CMOS process has been explored. The method is an extension of digital IDD test to analog circuits. We investigated detection rate of resistive open and short faults within a MOSFET device in several analog circuits implemented in 0.13?m CMOS technology. Input test signals are optimized for maximum detectability of introduced faults. Stimulus required for defect screening are DC signals which can be easily produced on-chip. It is shown in this paper that with respect to the used fault models the detection success rate for introduced faults is 100% for resistive shorts and 67% for resistive opens. This simple method is suitable for production testing, as a preliminary and complementary test of embedded analog circuits for early defect screening in highly integrated environment.
Citation:
Marco S. Dragic, Martin Margala, "Power Supply Current Test Approach for Resistive Fault Screening in Embedded Analog Circuits," dft, pp.124, 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'03), 2003
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