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17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'02)
Vancouver, BC, Canada
November 06-November 08
ISBN: 0-7695-1831-1
Table of Contents
Introduction
Session 1: Yield I
Session 2: Crosstalk Faults
Session 3: Self-Checking and ABFT
Guido Bertoni, Politecnico di Milano
Luca Breveglieri, Politecnico di Milano
Israel Koren, University of Massachusetts at Amherst
Paolo Maistri, Politecnico di Milano
Vincenzo Piuri, University of Milan
pp. 51
Jimson Mathew, Royal Institute of Technology
Elena Dubrova, Royal Institute of Technology
pp. 69
D. Marienfeld, University of Potsdam
V. Ocheretnij, University of Potsdam
M. Gössel, University of Potsdam
E. S. Sogomonyan, University of Potsdam
pp. 78
Session 4: Fault Simulation and Injection I
Horng-Bin Wang, National Tsing-Hua University
Shi-Yu Huang, National Tsing-Hua University
Jing-Reng Huang, National Tsing-Hua University
pp. 117
Session 5: Scan Design
Session 6: Test Application
F. Karimi, LTX Corporation
W. Meleis, Northeastern University
Z. Navabi, Northeastern University
F. Lombardi, Northeastern University
pp. 166
Session 7: Test Generation
Jennifer Dworak, Texas A&M University
James Wingfield, Texas A&M University
Brad Cobb, Texas A&M University
Sooryong Lee, Texas A&M University
Li-C. Wang, University of California at Santa Barbara
M. Ray Mercerl, Texas A&M University
pp. 177
Session 8: Concurrent Error Detection
F. Rodríguez, Universidad Politécnica de Valencia
J. C. Campelo, Universidad Politécnica de Valencia
J. J. Serrano, Universidad Politécnica de Valencia
pp. 225
F. Salice, Politecnico di Milano
M. G. Sami, Politecnico di Milano
R. Stefanelli, Politecnico di Milano
pp. 233
Session 9: Fault Simulation and Injection II
Lörinc Antoni, TIMA Laboratory and Budapest University of Technology and Economics
Régis Leveugle, TIMA Laboratory
Béla Fehér, Budapest University of Technology and Economics
pp. 245
S. Blanc, Polytechnic University of Valencia
J. Gracia, Polytechnic University of Valencia
P. J. Gil, Polytechnic University of Valencia
pp. 254
Session 10: Interconnect
F. Lombardi, Northeastern University
N. Park, Oklahoma State University
pp. 293
Session 11: Yield II
Bing Qiu, Concordia University
Yvon Savaria, Ecole Polytechnique de Montreal
Meng Lu, Ecole Polytechnique de Montreal
Chunyan Wang, Concordia University
Claude Thibeault, Ecole de Technologie Superieure
pp. 314
Session 12: System-on-Chip Test
Dan Zhao, State University of New York at Buffalo
Shambhu Upadhyaya, State University of New York at Buffalo
pp. 334
Session 13: Feasibility of CED
Session 14: Test
A. Castelnuovot, STMicroelectronics
A. Fin, Universita di Verona
F. Fummi, Universita di Verona
F. Sforza, STMicroelectronics
pp. 365
Witold A. Pleskacz, Warsaw University of Technology
Tomasz Borejko, Warsaw University of Technology
Wieslaw Kuzmicz, Warsaw University of Technology
pp. 390
V. Stopjaková, Slovak University of Technology
D. Mičušík, Slovak University of Technology
L.' Beňuscaron;ková, Comenius University
M. Margala, University of Rochester
pp. 408
Session 15: Reliable and Repairable Memories
M. Choi, Oklahoma State University
N. Park, Oklahoma State University
F. Lombardi, Northeastern University
Y. B. Kim, Northeastern University
V. Piuri, University of Milan
pp. 419
Y. Chang, Oklahoma State University
M. Choi, Oklahoma State University
N. Park, Oklahoma State University
F. Lombardi, Northeastern University
pp. 428
Author Index
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