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2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (2002)
Vancouver, BC, Canada
Nov. 6, 2002 to Nov. 8, 2002
ISBN: 0-7695-1831-1
TABLE OF CONTENTS
Introduction
pp. xiii
pp. 439
Session 1: Yield I
Arman Vassighi , University of Waterloo
Oleg Semenov , University of Waterloo
Manoj Sachdev , University of Waterloo
Ali Keshavarzi , Intel Corp
pp. 12
B. M. Maziarz , University of South Florida
V. K. Jain , University of South Florida
pp. 20
Session 2: Crosstalk Faults
Pierluigi Civera , Politecnico di Torino
Luca Macchiarulo , Politecnico di Torino
Massimo Violante , Politecnico di Torino
pp. 31
Hamidreza Hashempour , Northeastern University
Yong-Bin Kim , Northeastern University
Naphill Park , Oklahoma State University
pp. 40
Session 3: Self-Checking and ABFT
Guido Bertoni , Politecnico di Milano
Luca Breveglieri , Politecnico di Milano
Israel Koren , University of Massachusetts at Amherst
Paolo Maistri , Politecnico di Milano
Vincenzo Piuri , University of Milan
pp. 51
Cristiana Bolchini , Politecnico di Milano
Fabio Salice , Politecnico di Milano
Donatella Sciuto , Politecnico di Milano
pp. 60
Jimson Mathew , Royal Institute of Technology
Elena Dubrova , Royal Institute of Technology
pp. 69
D. Marienfeld , University of Potsdam
V. Ocheretnij , University of Potsdam
M. Gössel , University of Potsdam
E. S. Sogomonyan , University of Potsdam
pp. 78
Kartik Mohanram , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 87
Session 4: Fault Simulation and Injection I
R. Velazco , TIMA Laboratory
A. Corominas , TIMA Laboratory
P. Ferreyra , Universidad Nacional de C?rdoba
pp. 108
Horng-Bin Wang , National Tsing-Hua University
Shi-Yu Huang , National Tsing-Hua University
Jing-Reng Huang , National Tsing-Hua University
pp. 117
Session 5: Scan Design
Paul M. Rosinger , University of Southampton
Bashir M. Al-Hashimi , University of Southampton
Nicola Nicolici , McMaster University
pp. 129
Ranganathan Sankaralingam , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 138
Session 6: Test Application
Kedarnath J. Balakrishnan , University of Texas at Austin
Nur A. Touba , University of Texas at Austin
pp. 159
F. Karimi , LTX Corporation
W. Meleis , Northeastern University
Z. Navabi , Northeastern University
F. Lombardi , Northeastern University
pp. 166
Session 7: Test Generation
Jennifer Dworak , Texas A&M University
James Wingfield , Texas A&M University
Brad Cobb , Texas A&M University
Sooryong Lee , Texas A&M University
Li-C. Wang , University of California at Santa Barbara
M. Ray Mercerl , Texas A&M University
pp. 177
H. Hashempour , Northeastern University
F. J. Meyer , Northeastern University
F. Lombardi , Northeastern University
pp. 186
Ahmad A. Al-Yamani , Stanford University
Subhasish Mitra , Intel Corporation
Edward J. McCluskey , Stanford University
pp. 195
Session 8: Concurrent Error Detection
F. Rodríguez , Universidad Politécnica de Valencia
J. C. Campelo , Universidad Politécnica de Valencia
J. J. Serrano , Universidad Politécnica de Valencia
pp. 225
F. Salice , Politecnico di Milano
M. G. Sami , Politecnico di Milano
R. Stefanelli , Politecnico di Milano
pp. 233
Session 9: Fault Simulation and Injection II
Lörinc Antoni , TIMA Laboratory and Budapest University of Technology and Economics
Régis Leveugle , TIMA Laboratory
Béla Fehér , Budapest University of Technology and Economics
pp. 245
S. Blanc , Polytechnic University of Valencia
J. Gracia , Polytechnic University of Valencia
P. J. Gil , Polytechnic University of Valencia
pp. 254
Session 10: Interconnect
Susumu Horiguchi , Japan Advanced Institute of Science and Technology
Yasuyuki Miura , Communication Research Laboratory
pp. 275
X. Sun , University of Alberta
A. Alimohammad , University of Alberta
Pieter Trouborst , Nortel Networks
pp. 284
F. Lombardi , Northeastern University
N. Park , Oklahoma State University
pp. 293
Session 11: Yield II
Yuichi Hamamura , Hitachi, Ltd.
Kazunori Nemoto , Hitachi, Ltd.
Takaaki Kumazawa , Hitachi, Ltd.
Hisafumi Iwata , Hitachi, Ltd.
Kousuke Okuyama , Hitachi, Ltd.
Shiro Kamohara , Hitachi, Ltd.
Aritoshi Sugimoto , Hitachi, Ltd.
pp. 305
Bing Qiu , Concordia University
Yvon Savaria , Ecole Polytechnique de Montreal
Meng Lu , Ecole Polytechnique de Montreal
Chunyan Wang , Concordia University
Claude Thibeault , Ecole de Technologie Superieure
pp. 314
Session 12: System-on-Chip Test
Ozgur Sinanoglu , University of California at San Diego
Alex Orailoglu , University of California at San Diego
pp. 325
Dan Zhao , State University of New York at Buffalo
Shambhu Upadhyaya , State University of New York at Buffalo
pp. 334
Session 13: Feasibility of CED
Session 14: Test
A. Castelnuovot , STMicroelectronics
A. Fin , Universita di Verona
F. Fummi , Universita di Verona
F. Sforza , STMicroelectronics
pp. 365
M. Rebaudengo , Politecnico di Torino
M. Sonza Reorda , Politecnico di Torino
M. Violante , Politecnico di Torino
pp. 372
Witold A. Pleskacz , Warsaw University of Technology
Tomasz Borejko , Warsaw University of Technology
Wieslaw Kuzmicz , Warsaw University of Technology
pp. 390
Tian Xia , University of Rhode Island
Jien-Chung Lo , University of Rhode Island
pp. 399
V. Stopjaková , Slovak University of Technology
D. Mičušík , Slovak University of Technology
L.' Beňuscaron;ková , Comenius University
M. Margala , University of Rochester
pp. 408
Session 15: Reliable and Repairable Memories
M. Choi , Oklahoma State University
N. Park , Oklahoma State University
F. Lombardi , Northeastern University
Y. B. Kim , Northeastern University
V. Piuri , University of Milan
pp. 419
Y. Chang , Oklahoma State University
M. Choi , Oklahoma State University
N. Park , Oklahoma State University
F. Lombardi , Northeastern University
pp. 428
Author Index
Author Index (PDF)
pp. 437
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