Message from the Symposium Chairpersons

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Organizing Committee (PDF)

pp. xii

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Session 1: Wafer Scale

Advanced Fault-Tolerance Techniques for a Color Digital Camera-on-a-Chip (Abstract)

Israel Koren, University of Massachusetts

Zahava Koren, University of Massachusetts

Glenn Chapman, Simon Fraser University

pp. 0003

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Challenges Facing Practical DFT for MEMS (Abstract)

S.K. Tewksbury, Stevens Institute of Technology

pp. 0011

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Design of a Self-Correcting Active Pixel Sensor (Abstract)

Yves Audet, Ecole Polytechnique

Glenn H. Chapman, Simon Fraser University

pp. 0018

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Session 2: Yield

Yield-Reliability Modeling for Fault Tolerant Integrated Circuits (Abstract)

Thomas S. Barnett, Auburn University

Adit D. Singh, Auburn University

Victor P. Nelson, Auburn University

pp. 0029

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A Simple via Duplication Tool for Yield Enhancement (Abstract)

Neil Harrison, Philips Semiconductors

pp. 0039

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Relation between Reliability and Yield of IC's Based on Discrete Defect Distribution Model (Abstract)

Tianxu Zhao, Xidian University

Yue Hao, Xidian University

Peijun Ma, Xidian University

Taifeng Chen, Xidian University

pp. 0048

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Session 3: Dependable Design

An On-Chip Detection Circuit for the Verification of IC Supply Connections (Abstract)

Hans Manhaeve, Q-Star Test nv

Stefaan Kerckenaere, Q-Star Test nv

pp. 0057

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On-Line Error Detectable Carry-Free Adder Design (Abstract)

P.K. Lala, University of Arkansas

A. Walker, North Carolina A&T State University

pp. 0066

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Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System (Abstract)

Shugang Wei, Gunma University

Kensuke Shimizu, Gunma University

pp. 0072

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Enhanced Concurrent Error Correcting Arithmetic Unit Design Using Alternating Logic (Abstract)

Tat Ngai, University of Texas at Austin

Earl E. Swartzlander Jr, University of Texas at Austin

Chen He, University of Texas at Austin

Inc. Motorola

pp. 0078

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High Level Modifications of VHDL Descriptions for On-Line Test or Fault Tolerance (Abstract)

R. Leveugle, TIMA Laboratory

R. Cercueil, TIMA Laboratory

pp. 0084

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Session 4: Testing Techniques 1

Embedded Core Testing Using Broadcast Test Architecture (Abstract)

J. H. Jiang, National Chung Cheng University

S. C. Chang, National Chung Cheng University

W. B Jone, University of Cincinnati

pp. 0095

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Analyzing BIST Robustness (Abstract)

Janusz Sosnowski, Warsaw University of Technology

pp. 0104

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Test Pattern Decompression Using a Scan Chain (Abstract)

Ondrej Novak, Technical University Liberec

Jiri Nosek, Technical University Liberec

pp. 0110

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Reducing Power Dissipation during At-Speed Test Application (Abstract)

Xiaowei Li, Chinese Academy of Sciences

Huawei Li, Chinese Academy of Sciences

Yinghua Min, Chinese Academy of Sciences

pp. 0116

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Session 5: Fault-Tolerance in Arrays

Permanent Fault Repair for FPGAs with Limited Redundant Area (Abstract)

Shu-Yi Yu, Stanford University

Edward J. McCluskey, Stanford University

pp. 0125

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Built-in Self-Reconfiguring Systems for Fault Tolerant Mesh-Connected Processor Arrays by Direct Spare Replacement (Abstract)

Itsuo Takanami, Ichinoseki National College of Technology

pp. 0134

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ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication (Abstract)

Nobuo Tsuda, Kanazawa Institute of Technology

pp. 0143

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On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router (Abstract)

John M. Emmert, UNCC

Jason A. Cheatham, UNCC

pp. 0149

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Session 6: Fault Detection

Novel Approaches for Fault Detection in Two-Dimensional Combinational Arrays (Abstract)

X.T. Chen, Lucent Technologies

W.K. Huang, Fudan Univ

N. Park, Oklahoma State Univ

F.J. Meyer, Northeastern Univ

F. Lombardi, Northeastern Univ

pp. 0161

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A Software Methodology for Detecting Hardware Faults in VLIW Data Paths (Abstract)

C. Bolchini, Politecnico di Milano

F. Salice, Politecnico di Milano

pp. 0170

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Efficient Parity Prediction in FPGA (Abstract)

Seok-Bum Ko, University of Rhode Island

Xia Tian, University of Rhode Island

Jien-Chung Lo, University of Rhode Island

pp. 0176

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Procedure Call Duplication: Minimization of Energy Consumption with Constrained Error Detection Latency (Abstract)

Nahmsuk Oh, Stanford University

Edward J. McCluskey, Stanford University

pp. 0182

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A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application (Abstract)

Session 7: FPGA Based Applications

Monica Alderighi, Istituto di Fisica Cosmica "G. Occhialini"

Fabio Casini, Istituto di Fisica Cosmica "G. Occhialini"

Sergio D'Angelo, Istituto di Fisica Cosmica "G. Occhialini"

Davide Salvi, Istituto di Fisica Cosmica "G. Occhialini"

Giacomo R. Sechi, Istituto di Fisica Cosmica "G. Occhialini"

pp. 0191

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Idle Cycles Based Concurrent Error Detection of RC6 Encryption (Abstract)

Kaijie Wu, Polytechnic University

Ramesh Karri, Polytechnic University

pp. 0200

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Fast Run-Time Fault Location in Dependable FPGA-Based Applications (Abstract)

Wei-Je Huang, Stanford University

Subhasish Mitra, Stanford University

Edward J. McCluskey, Stanford University

pp. 0206

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Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability (Abstract)

Jayabrata Ghosh-Dastidar, University of Texas

Nur A. Touba, University of Texas

pp. 0215

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Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules (Abstract)

Xiaoling Sun, University of Alberta

Jian Xu, University of Alberta

Pieter Trouborst, Nortel Networks

pp. 0221

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Session 8: Fault Injection

Comparison and Application of Different VHDL-Based Fault Injection Techniques (Abstract)

J. Gracia, Universidad Polit?cnica de Valencia. Spain

J.C. Baraza, Universidad Polit?cnica de Valencia. Spain

D. Gil, Universidad Polit?cnica de Valencia. Spain

P.J. Gil, Universidad Polit?cnica de Valencia. Spain

pp. 0233

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A Low-Cost Hardware Approach to Dependability Validation of Ips (Abstract)

R. Leveugle, TIMA Laboratory

pp. 0242

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Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits (Abstract)

P. Civera, Politecnico di Torino

L. Macchiarulo, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

M. Violante, Politecnico di Torino

pp. 0250

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Upset-Like Fault Injection in VHDL Descriptions: A Method and Preliminary Results (Abstract)

R. Velazco, TIMA Laboratory

R. Leveugle, TIMA Laboratory

O. Calvo, Universidad de las Islas Baleares (U.I.B.)

pp. 0259

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Session 9: Testing Techniques 2

Parallel Testing of Multi-port Static Random Access Memories for BIST (Abstract)

F. Karimi, Northeastern University

F. Lombardi, Northeastern University

pp. 0271

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A Speed-Dependent Approach for Delta IDDQ Implementation (Abstract)

Paul Lee, LSI Logic HongKong

Alfred Chen, LSI Logic HongKong

Dilip Mathew, LSI Logic HongKong

pp. 0280

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Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field (Abstract)

Hiroyuki Yotsuyanagi, Univ. of Tokushima

Masaki Hashizume, Univ. of Tokushima

Taisuke Iwakiri, Univ. of Tokushima

Masahiro Ichimiya, Univ. of Tokushima

Takeomi Tamesada, Univ. of Tokushima

pp. 0287

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Session 10: Error Correcting Codes

Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities (Abstract)

Kazuteru Namba, Tokyo Institute of Technology

Eiji Fujiwara, Tokyo Institute of Technology

pp. 0299

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Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications (Abstract)

Amir Kazéminéjad, Universit? Paris XI

Eric Belhaire, Universit? Paris XI

pp. 0308

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Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes (Abstract)

Stanislaw J. Piestrak, Wroclaw University of Technology

Abbas Dandache, University of Metz

Fabrice Monteiro, University of Metz

pp. 0314

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Session 11: Mixed Signal Circuits

Sensitivity and Reliability Evaluation for Mixed-Signal ICs under Electromigration and Hot-Carrier Effects (Abstract)

Xiangdong Xuan, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 0323

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A Step Response Based Mixed-Signal BIST Approach (Abstract)

Alvernon Walker, North Carolina A&T State University

pp. 0329

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Analog BIST Generator for ADC Testing (Abstract)

S. Bernard, University of Montpellier

F. Azaïs, University of Montpellier

Y. Bertrand, University of Montpellier

M. Renovell, University of Montpellier

pp. 0338

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Reliability Enhancement of Analog-to-Digital Converters (ADCs) (Abstract)

Mandeep Singh, University of Massachusetts

Israel Koren, University of Massachusetts

pp. 0347

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Session 12: Defect Analysis

Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects (Abstract)

C. Metra, University of Bologna

S. Di Francescantonio, University of Bologna

B. Ricco', University of Bologna

T.M. Mak, Intel Corporation

pp. 0357

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Defect Analysis and a New Fault Model for Multi-port SRAMs (Abstract)

Pradeep Nagaraj, Qualcomm CDMA Technologies

Shambhu Upadhaya, SUNY

Kamran Zarrineh, SUN Microelectronics

Dean Adams, IBM Microelectronics

pp. 0366

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Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell Library (Abstract)

Mykola Blyzniuk, Lviv Polytechnic National University

Irena Kazymyra, Lviv Polytechnic National University

pp. 0375

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CMOS Standard Cells Characterization for Defect Based Testing (Abstract)

Witold A. Pleskacz, Warsaw University of Technology

Dominik Kasprowicz, Warsaw University of Technology

Tomasz Oleszczak, Warsaw University of Technology

Wieslaw Kuzmicz, Warsaw University of Technology

pp. 0384

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Session 13: Self-Checking and Fail-Safe Circuits

Survivable Self-Checking Sequential Circuits (Abstract)

A. Matrosova, Tomsk State University

S. Ostanin, Tel-Aviv University

I. Levin, Tel-Aviv University

pp. 0395

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Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines (Abstract)

M. Ottavi, University of Rome

G. C. Cardarilli, University of Rome

D. Cellitti, University of Rome

S. Pontarelli, University of Rome

M. Re, University of Rome

A. Salsano, University of Rome

pp. 0403

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Fail-Safe Synchronization Circuit for Duplicated Systems (Abstract)

Eleftherios Kolonis, iROC Technologies

Michael Nicolaidis, iROC Technologies

pp. 0412

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How to Tune the MTTF of a Fail-Silent System (Abstract)

Andreas Steininger, Vienna University of Technology

Christoph Scherrer, Vienna University of Technology

pp. 0418

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Session 14: Fault-Tolerant Techniques

Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture (Abstract)

Ramesh Karri, Polytechnic University

Kaijie Wu, Polytechnic University

Piyush Mishra, Polytechnic University

Yongkook Kim, IBM Corporation

pp. 0427

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On Variable-Shift-Based Fault Compensation of Fuzzy Controllers (Abstract)

Naotake Kamiura, Himeji Institute of Technology

Masashi Tomita, Himeji Institute of Technology

Teijiro Isokawa, Himeji Institute of Technology

Nobuyuki Matsui, Himeji Institute of Technology

pp. 0436

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On-Line Fault Tolerance for FPGA Interconnect with Roving STARs (Abstract)

John Emmert, UNC Charlotte

Stanley Baumgart, UNC Charlotte

Pankaj Kataria, UNC Charlotte

Andrew Taylor, UNC Charlotte

Charles Stroud, UNC Charlotte

Miron Abramovici, Agere Systems

pp. 0445

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System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology (Abstract)

S. Pontarelli, University of Rome

G.C. Cardarilli, University of Rome

A. Malvoni, University of Rome

M. Ottavi, University of Rome

M. Re, University of Rome

A. Salsano, University of Rome

pp. 0455

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Performance Evaluation of Checksum-Based ABFT (Abstract)

Ahmad A. Al-Yamani, Stanford University

Nahmsuk Oh, Stanford University

Edward J. McCluskey, Stanford University

pp. 0461

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Author Index (PDF)

pp. 0467