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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01)
San Francisco, California
October 24-October 26
ISBN: 0-7695-1203-8
Table of Contents
Session 1: Wafer Scale
Israel Koren, University of Massachusetts
Zahava Koren, University of Massachusetts
Glenn Chapman, Simon Fraser University
pp. 0003
Session 2: Yield
Session 3: Dependable Design
P.K. Lala, University of Arkansas
A. Walker, North Carolina A&T State University
pp. 0066
Session 4: Testing Techniques 1
J. H. Jiang, National Chung Cheng University
S. C. Chang, National Chung Cheng University
W. B Jone, University of Cincinnati
pp. 0095
Ondrej Novak, Technical University Liberec
Jiri Nosek, Technical University Liberec
pp. 0110
Xiaowei Li, Chinese Academy of Sciences
Huawei Li, Chinese Academy of Sciences
Yinghua Min, Chinese Academy of Sciences
pp. 0116
Session 5: Fault-Tolerance in Arrays
Session 6: Fault Detection
X.T. Chen, Lucent Technologies
W.K. Huang, Fudan Univ
N. Park, Oklahoma State Univ
F.J. Meyer, Northeastern Univ
F. Lombardi, Northeastern Univ
pp. 0161
Seok-Bum Ko, University of Rhode Island
Xia Tian, University of Rhode Island
Jien-Chung Lo, University of Rhode Island
pp. 0176
Session 7: FPGA Based Applications
Monica Alderighi, Istituto di Fisica Cosmica "G. Occhialini"
Fabio Casini, Istituto di Fisica Cosmica "G. Occhialini"
Sergio D'Angelo, Istituto di Fisica Cosmica "G. Occhialini"
Davide Salvi, Istituto di Fisica Cosmica "G. Occhialini"
Giacomo R. Sechi, Istituto di Fisica Cosmica "G. Occhialini"
pp. 0191
Session 8: Fault Injection
J. Gracia, Universidad Polit?cnica de Valencia. Spain
J.C. Baraza, Universidad Polit?cnica de Valencia. Spain
D. Gil, Universidad Polit?cnica de Valencia. Spain
P.J. Gil, Universidad Polit?cnica de Valencia. Spain
pp. 0233
P. Civera, Politecnico di Torino
L. Macchiarulo, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
M. Violante, Politecnico di Torino
pp. 0250
Session 9: Testing Techniques 2
Session 10: Error Correcting Codes
Session 11: Mixed Signal Circuits
S. Bernard, University of Montpellier
F. Azaïs, University of Montpellier
Y. Bertrand, University of Montpellier
M. Renovell, University of Montpellier
pp. 0338
Session 12: Defect Analysis
Witold A. Pleskacz, Warsaw University of Technology
Dominik Kasprowicz, Warsaw University of Technology
Tomasz Oleszczak, Warsaw University of Technology
Wieslaw Kuzmicz, Warsaw University of Technology
pp. 0384
Session 13: Self-Checking and Fail-Safe Circuits
A. Matrosova, Tomsk State University
S. Ostanin, Tel-Aviv University
I. Levin, Tel-Aviv University
pp. 0395
M. Ottavi, University of Rome
G. C. Cardarilli, University of Rome
D. Cellitti, University of Rome
S. Pontarelli, University of Rome
M. Re, University of Rome
A. Salsano, University of Rome
pp. 0403
Andreas Steininger, Vienna University of Technology
Christoph Scherrer, Vienna University of Technology
pp. 0418
Session 14: Fault-Tolerant Techniques
Naotake Kamiura, Himeji Institute of Technology
Masashi Tomita, Himeji Institute of Technology
Teijiro Isokawa, Himeji Institute of Technology
Nobuyuki Matsui, Himeji Institute of Technology
pp. 0436
John Emmert, UNC Charlotte
Stanley Baumgart, UNC Charlotte
Pankaj Kataria, UNC Charlotte
Andrew Taylor, UNC Charlotte
Charles Stroud, UNC Charlotte
Miron Abramovici, Agere Systems
pp. 0445
S. Pontarelli, University of Rome
G.C. Cardarilli, University of Rome
A. Malvoni, University of Rome
M. Ottavi, University of Rome
M. Re, University of Rome
A. Salsano, University of Rome
pp. 0455
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