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IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'00)
Yamanashi, Japan
October 25-October 27
ISBN: 0-7695-0719-0
Table of Contents
Session 1: Yield Analysis and Modeling
Rajnish K. Prasad, University of Massachusetts at Amherst
Israel Koren, University of Massachusetts at Amherst
pp. 3
Xiaohong Jiang, Japan Advanced Institute of Science and Technology
Susumu Horiguchi, Japan Advanced Institute of Science and Technology
Yue Hao, Xidian University
pp. 21
Session 2: Yield Enhancement Techniques
N. Park, Oklahoma State University
F. Meyer, Northeastern University
F. Lombardi, Northeastern University
pp. 47
Israel Koren, University of Massachusetts at Amherst
Zahava Koren, University of Massachusetts at Amherst
Glenn Chapman, Simon Fraser University
pp. 56
Session 3: Wafer Scale/Large Area Systems
Markus Rudack, University of Hannover
Michael Redeker, University of Hannover
Dieter Treytnar, University of Hannover
Ole Mende, University of Hannover
Klaus Herrmann, University of Hannover
pp. 78
Xiaohong Jiang, Japan Advanced Institute of Science and Technology
Susumu Horiguchi, Japan Advanced Institute of Science and Technology
pp. 96
Session 4: Fault-Tolerant Interconnections
Session 5: Fault-Tolerant Systems
Monica Alderighi, Consiglio Nazionale delle Ricerche
Sergio D'Angelo, Consiglio Nazionale delle Ricerche
Giacomo R. Sechi, Consiglio Nazionale delle Ricerche
Cecilia Metra, Universita' di Bologna
pp. 155
Jae-Hyuck Kwak, University of Texas at Austin
Earl E. Swartzlander, Jr., University of Texas at Austin
Vincenzo Piuri, Politecnico di Milano
pp. 164
G.C. Cardarilli, University of Rome ?Tor Vergata?
A. Salsano, University of Rome ?Tor Vergata?
P. Marinucci, Consortium ULISSE
M. Ottavi, Consortium ULISSE
pp. 173
Session 6: Error Coding
Masato Kitakami, Chiba University
Hongyuan Chen, Tokyo Institute of Technology
Eiji Fujiwara, Tokyo Institute of Technology
pp. 183
Yasunao Katayama, IBM Research, Tokyo Research Laboratory
Yasushi Negishi, IBM Research, Tokyo Research Laboratory
Sumio Morioka, IBM Research, Tokyo Research Laboratory
pp. 201
Session 7: Reconfiguration and Repair
A. Benso, Politecnico di Torino
S. Chiusano, Politecnico di Torino
P. Prinetto, Politecnico di Torino
P. Simonotti, Politecnico di Torino
G. Ugo, Politecnico di Torino
pp. 231
Session 8: Online Testing
Session 9: Built-In Self-Test
Gert Jervan, Link?ping University
Zebo Peng, Link?ping University
Raimund Ubar, Tallinn Technical University
pp. 283
G. Biasoli, Politecnico di Milano
F. Ferrandi, Politecnico di Milano
D. Sciuto, Politecnico di Milano
A. Fin, Universit? di Verona
F. Fummi, Universit? di Verona
pp. 292
Chuang Cheng, National Tsing Hua University
Chih-Tsun Huang, National Tsing Hua University
Jing-Reng Huang, National Tsing Hua University
Cheng-Wen Wu, National Tsing Hua University
Chen-Jong Wey, Global UniChip Corp.
Ming-Chang Tsai, Global UniChip Corp.
pp. 299
Session 10: Testing Strategies
N. Park, Oklahoma State University
S.J. Ruiwale, Northeastern University
F. Lombardi, Northeastern University
pp. 311
C.H. Cheng, National Chung Cheng University
J.S. Wang, National Chung Cheng University
S.C. Chang, National Chung Cheng University
W.B. Jone, New Mexico Tech
pp. 329
Janusz Sosnowski, Warsaw University of Technology
Tomasz Wabia, Warsaw University of Technology
Tomasz Bech, Warsaw University of Technology
pp. 338
Session 11: IDDQ Testing
Masaki Hashizume, University of Tokushima
Hiroyuki Yotsuyanagi, University of Tokushima
Takeomi Tamesada, University of Tokushima
Masashi Takeda, University of Tokushima
pp. 367
Shengli Li, University of Rhode Island
Kai Zhang, University of Rhode Island
Jien-Chung Lo, University of Rhode Island
pp. 376
Session 12: Fault Injection
Andrea Baldini, Politecnico di Torino
Alfredo Benso, Politecnico di Torino
Silvia Chiusano, Politecnico di Torino
Paolo Prinetto, Politecnico di Torino
pp. 387
J. C. Baraza, Universidad Polit?cnica de Valencia
J. Gracia, Universidad Polit?cnica de Valencia
D. Gil, Universidad Polit?cnica de Valencia
P.J. Gil, Universidad Polit?cnica de Valencia
pp. 396
Lörinc Antoni, TIMA Laboratory and Budapest University of Technology and Economics
Régis Leveugle, TIMA Laboratory
Béla Fehér, Budapest University of Technology and Economics
pp. 405
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