CSDL - Proceedings D

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Acknowledgments (PDF)

pp. xi

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Keynote Address

Dealing with Defects in Very Deep Submicron Chips and Beyond

Session 1: Yield and Defect Density

Binning for IC Quality: Experimental Studies on the SEMATECH Data (Abstract)

A.D. Singh

D.R. Lakin, II

G. Sinha

P. Nigh

pp. 4

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A Yield Improvement Program Using Process Control and Process Optimization for Particle Reduction Using In Situ Particle Monitoring on a Semitool Magnum (Abstract)

pp. 11

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Management of Critical Areas and Defectivity Data for Yield Trend Modeling (Abstract)

Sandrine Barberan, STMicroelectronics

Frederic Duvivier, STMicroelectronics

pp. 17

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Session 2: Layout and Critical Area

Yield and Routing Objectives in Floorplanning (Abstract)

Israel Koren, University of Massachusetts

Zahava Koren, University of Massachusetts

pp. 28

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Orphan Metal Removal as an Element of DFM (Abstract)

Neil Harrison, Philips Semiconductors

pp. 37

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A Comparison of Efficient Dot Throwing and Shape Shifting Extra Material Critical Area Estimation (Abstract)

Gerard A. Allan, University of Edinburgh

pp. 44

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Invited Presentation

Hardware Fault-Tolerance Requirements for Very Deep Submicron

Session 3: Reliability Enhancement

A Fast Minimum Layout Perturbation Algorithm for Electromigration Reliability Enhancement (Abstract)

Zhan Chen, Intel Corp.

Fook-Luen Heng, IBM

pp. 56

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FPGA Design for Decimeter Scale Integration (DMSI) (Abstract)

G.H. Chapman

pp. 64

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Process Variations and their Impact on Circuit Operation (Abstract)

Suriyaprakash Natarajan, University of Southern California

Melvin A. Breuer, University of Southern California

Sandeep K. Gupta, University of Southern California

pp. 73

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Session 4: Defect and Fault Analysis

Comprehensive Defect Analysis and Defect Coverage of CMOS Circuits (Abstract)

D. Al-Khalili, Royal Military College of Canada

S. Adham, Royal Military College of Canada

C. Rozon, Royal Military College of Canada

M. Hossain, Royal Military College of Canada

D. Racz, Royal Military College of Canada

pp. 84

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Characterization of CMOS Defects using Transient Signal Analysis (Abstract)

James F. Plusquellic, University of Maryland

Donald M. Chiarulli, University of Pittsburgh

Steven P. Levitan, University of Pittsburgh

pp. 93

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Accurate Fault Modeling and Fault Simulation of Resistive Bridges (Abstract)

Vijay Sar-Dessai, Texas A&M University

D. M. H. Walker, Texas A&M University

pp. 102

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Functional Verification Coverage vs. Physical Stuck-at Fault Coverage (Abstract)

Xiao Sun, Applied Micro Circuits Corporation

Carmie Hull, Applied Micro Circuits Corporation

pp. 108

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An Integrated HW and SW Fault Injection Environment for Real-Time Systems (Abstract)

A. Benso, Politecnico di Torino

M. Rebaudengo, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

P.L. Civera, Politecnico di Torino

pp. 117

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Panel Session: Fault Tolerance

Needs and Perspectives

Session 5: Testing Techniques

Increasing Current Testing Resolution (Abstract)

Claude Thibeault, ?cole de Technologie Sup?rieure

pp. 126

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On-Chip Test Embedding for Multi-Weighted Random LFSRs (Abstract)

pp. 135

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Session 6: Testing of Regular Structures

A New Method for Testing EEPLA's (Abstract)

Avinash Munshi, Texas A&M University

Fred J. Meyer, Texas A&M University

Fabrizio Lombardi, Northeastern University

pp. 146

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C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications (Abstract)

T. Haniotakis, University of Patras

D. Nikolos, University of Patras

Y. Tsiatouhas, University of Athens

pp. 155

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On the Complexity of Sequential Testing in Configurable FPGAs (Abstract)

Wenyi Feng, Texas A&M University

Fred J. Meyer, Texas A&M University

Wei Kang Huang, Fudan University

Fabrizio Lombardi, Northeastern University

pp. 164

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Session 7: Concurrent Testing Techniques

Signal Coding Technique and CMOS Gates for Strongly Fault-Secure Combinational Functional Blocks (Abstract)

pp. 174

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Systematic AUED Codes for Self-Checking Architectures (Abstract)

pp. 183

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Challenges of Built-In Current Sensor Designs (Abstract)

Yu-Yau Guo, The University of Rhode Island

Jien-Chung Lo, The University of Rhode Island

pp. 192

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Session 8: Fault Diagnosis

On the Current Behavior of Faulty and Fault-Free ICs and the Impact on Diagnosis (Abstract)

Claude Thibeault, ?cole de Technologie Sup?rieure

Luc Boisvert, CAE ELECTRONIQUE LTEE

pp. 202

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A Systematic Approach for Diagnosing Multiple Delay Faults (Abstract)

Jayabrata Ghosh Dastidar, University of Texas at Austin

Nur A. Touba, University of Texas at Austin

pp. 211

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Diagnosis of Scan Chain Failures (Abstract)

Yuejian Wu, Nortern Telecom

pp. 217

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Session 9: Fault-Tolerant Designs I

Error-Correcting Goldschmidt Dividers Using Time Shared TMR (Abstract)

W. Lynn Gallagher, The University of Texas at Austin

Earl E. Swartzlander, Jr., The University of Texas at Austin

pp. 224

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Fault-Tolerant Voting Mechanism and Recovery Scheme for TMR FPGA-Based Systems (Abstract)

pp. 233

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Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure (Abstract)

Daniel Audet, Universit? du Qu?bec ? Chicoutimi

Steve Masson, Universit? du Qu?bec ? Chicoutimi

Yvon Savaria, Ecole Polytechnique de Montr?al

pp. 241

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Session 10: Fault-Tolerant Designs II

Transient and Intermittent Fault Recovery without Rollback (Abstract)

Samuel Norman Hamilton, University of California at San Diego

Alex Orailoglu, University of California at San Diego

pp. 252

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Highly Reliable Systems with Differential Built-In Current Sensors (Abstract)

Jien-Chung Lo, The University of Rhode Island

pp. 261

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A Silicon Compiler for Fault-Tolerant ROMs (Abstract)

pp. 270

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Self-Reconfiguration Scheme of 3D-Mesh Arrays (Abstract)

Susumu Horiguchi, Japan Advanced Institute of Science and Technology

Issei Numata, Japan Advanced Institute of Science and Technology

pp. 276

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Session 11: High-Level Synthesis of Reliable Systems

A System for Evaluating On-Line Testability at the RT-level (Abstract)

S. Chiusano, Politecnico di Torino

F. Corno, Politecnico di Torino

M. Sonza Reorda, Politecnico di Torino

R. Vietti, Politecnico di Torino

pp. 284

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High-level Synthesis of Data Paths with Concurrent Error Detection (Abstract)

Anna Antola, Politecnico di Milano

Vincenzo Piuri, Politecnico di Milano

Mariagiovanna Sami, Politecnico di Milano

pp. 292

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Graceful Degradation in Synthesis of VLSI ICs (Abstract)

Alex Orailoglu, University of California at San Diego

pp. 301

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Designing for Yield: A Defect-Tolerant Approach to High-Level Synthesis (Abstract)

M. Broglia, Politecnico di Milano

G. Buonanno, Politecnico di Milano

M.G. Sami, Politecnico di Milano

M. Selvini, Politecnico di Milano

pp. 312

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High-Level BIST Synthesis for Delay Testing (Abstract)

Xiaowei Li, The University of Hong Kong

Paul Y.S. Cheung, The University of Hong Kong

pp. 318

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Session 12: Yield and Reliability Issues of Analog and Mixed Signal Circuits

Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCs (Abstract)

Andrea Boni, University of Parma

Andrea Pierazzi, University of Parma

pp. 326

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Specification-Driven Test Design for Analog Circuits (Abstract)

Pramodchandran N. Variyam, Georgia Institute of Technology

Abhijit Chatterjee, Georgia Institute of Technology

pp. 335

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Modular Fault Simulation of Mixed Signal Circuits with Fault Ranking by Severity (Abstract)

Alfred V. Gomes, Georgia Institute of Technology, Atlanta.

Ramakrishna Voorakaranam, Georgia Institute of Technology, Atlanta.

Abhijit Chatterjee, Georgia Institute of Technology, Atlanta.

pp. 341

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BIST Module for Mixed-Signal Circuits (Abstract)

S. Demidenko, Singapore Polytechnic and National Academy of Sciences of Belarus

V. Piuri, Politecnico di Milano

V. Yarmolik, Belarusian State University of Informatics and Radio Electronics

A. Shmidman, Belarusian State University of Informatics and Radio Electronics

pp. 349

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Author Index (PDF)

pp. 355