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1998 International Symposium on Defect and Fault Tolerance in VLSI Systems
Austin, Texas
November 02-November 04
ISBN: 0-8186-8832-7
Table of Contents
Keynote Address
Dealing with Defects in Very Deep Submicron Chips and Beyond
Session 1: Yield and Defect Density
Session 2: Layout and Critical Area
Invited Presentation
Hardware Fault-Tolerance Requirements for Very Deep Submicron
Session 3: Reliability Enhancement
Suriyaprakash Natarajan, University of Southern California
Melvin A. Breuer, University of Southern California
Sandeep K. Gupta, University of Southern California
pp. 73
Session 4: Defect and Fault Analysis
D. Al-Khalili, Royal Military College of Canada
S. Adham, Royal Military College of Canada
C. Rozon, Royal Military College of Canada
M. Hossain, Royal Military College of Canada
D. Racz, Royal Military College of Canada
pp. 84
Xiao Sun, Applied Micro Circuits Corporation
Carmie Hull, Applied Micro Circuits Corporation
pp. 108
A. Benso, Politecnico di Torino
M. Rebaudengo, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
P.L. Civera, Politecnico di Torino
pp. 117
Panel Session: Fault Tolerance
Needs and Perspectives
Session 5: Testing Techniques
Session 6: Testing of Regular Structures
Avinash Munshi, Texas A&M University
Fred J. Meyer, Texas A&M University
Fabrizio Lombardi, Northeastern University
pp. 146
Wenyi Feng, Texas A&M University
Fred J. Meyer, Texas A&M University
Wei Kang Huang, Fudan University
Fabrizio Lombardi, Northeastern University
pp. 164
Session 7: Concurrent Testing Techniques
Yu-Yau Guo, The University of Rhode Island
Jien-Chung Lo, The University of Rhode Island
pp. 192
Session 8: Fault Diagnosis
Session 9: Fault-Tolerant Designs I
Daniel Audet, Universit? du Qu?bec ? Chicoutimi
Steve Masson, Universit? du Qu?bec ? Chicoutimi
Yvon Savaria, Ecole Polytechnique de Montr?al
pp. 241
Session 10: Fault-Tolerant Designs II
Samuel Norman Hamilton, University of California at San Diego
Alex Orailoglu, University of California at San Diego
pp. 252
Susumu Horiguchi, Japan Advanced Institute of Science and Technology
Issei Numata, Japan Advanced Institute of Science and Technology
pp. 276
Session 11: High-Level Synthesis of Reliable Systems
S. Chiusano, Politecnico di Torino
F. Corno, Politecnico di Torino
M. Sonza Reorda, Politecnico di Torino
R. Vietti, Politecnico di Torino
pp. 284
M. Broglia, Politecnico di Milano
G. Buonanno, Politecnico di Milano
M.G. Sami, Politecnico di Milano
M. Selvini, Politecnico di Milano
pp. 312
Xiaowei Li, The University of Hong Kong
Paul Y.S. Cheung, The University of Hong Kong
pp. 318
Session 12: Yield and Reliability Issues of Analog and Mixed Signal Circuits
Alfred V. Gomes, Georgia Institute of Technology, Atlanta.
Ramakrishna Voorakaranam, Georgia Institute of Technology, Atlanta.
Abhijit Chatterjee, Georgia Institute of Technology, Atlanta.
pp. 341
S. Demidenko, Singapore Polytechnic and National Academy of Sciences of Belarus
V. Piuri, Politecnico di Milano
V. Yarmolik, Belarusian State University of Informatics and Radio Electronics
A. Shmidman, Belarusian State University of Informatics and Radio Electronics
pp. 349
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