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1996 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT'96)
Boston, MA
November 06-November 08
ISBN: 0-8186-7545-4
Table of Contents
Session 1: Defect Avoidance
W.B. Culbertson, Hewlett-Packard Laboratories
R. Amerson, Hewlett-Packard Laboratories
R.J. Carter, Hewlett-Packard Laboratories
P. Kuekes, Hewlett-Packard Laboratories
G. Snider, Hewlett-Packard Laboratories
pp. 2
G.H. Chapman, Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
B. Dufort, Sch. of Eng. Sci., Simon Fraser Univ., Burnaby, BC, Canada
pp. 11
Session 2: Yield Prediction
C.H. Ouyang, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W.A. Pleskacz, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
W. Maly, Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 21
Session 3: Yield and Reliability Enhancement
A. Venkataraman, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
I. Koren, Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
pp. 68
W. Maly, Carnegie Mellon Univ., Pittsburgh, PA, USA
C. Ouyang, Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Ghosh, Carnegie Mellon Univ., Pittsburgh, PA, USA
S. Maturi, Carnegie Mellon Univ., Pittsburgh, PA, USA
pp. 86
Session 4: Layout-Driven Test
Tong Liu, Actel Corp., Sunnyvale, CA, USA
Xiaotao Chen, Actel Corp., Sunnyvale, CA, USA
F. Lombardi, Actel Corp., Sunnyvale, CA, USA
J. Salinas, Actel Corp., Sunnyvale, CA, USA
pp. 105
Session 5: Process Data Analysis
F. Joel Ferguson, University of California, Santa Cruz
Jianlin Yu, University of California, Santa Cruz
pp. 149
Session 6: Test And Diagnosis
C. Thibeault, Ecole de Technologie Superieure
A. Payeur, Ecole de Technologie Superieure
pp. 185
Session 7: Self-Test and Self-Checking Designs
P.K. Lala, Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
S. Yang, Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
F. Busaba, Dept. of Electr. Eng., North Carolina A&T State Univ., Greensboro, NC, USA
pp. 195
Cecilia Metra, DEIS - Universita' di Bologna
Michele Favalli, DEIS - Universita' di Bologna
Bruno Ricco, DEIS - Universita' di Bologna
pp. 204
Cecilia Metra, DEIS - Universita' di Bologna
Michele Favalli, DEIS - Universita' di Bologna
Bruno Ricco, DEIS - Universita' di Bologna
pp. 213
Session 8: Fault-Tolerant Structuies
W.L. Gallagher, Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
E.E. Swartzlander, Jr., Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
pp. 240
C. Bolchini, Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
G. Buonanno, Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
D. Sciuto, Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
R. Stefanelli, Dipt. di Elettronica e Inf., Politecnico di Milano, Italy
pp. 258
Session 9: Reliable Circuit Synthesis
Jien-Chung Lo, The University of Rhode Island
Masato Kitakami, Tokyo Institute of Technology
Eiji Fujiwara, Tokyo Institute of Technology
pp. 286
Kyosun Kim, University of Massachusetts
Ramesh Karri, University of Massachusetts
Miodrag Potkonjak, University of California, Los Angeles
pp. 295
X. Wendling, Laboratoire INPG/CSI
R. Rochet, Laboratoire INPG/CSI
R. Leveugle, Laboratoire INPG/CSI
pp. 304
Session 10: Fault-Tolerance Approaches
S. R. Goldberg, State University of New York at Buffalo
S. J. Upadhyaya, State University of New York at Buffalo
W. K. Fuchs, Purdue University
pp. 318
G.A. Mojoli, Dipt. di Fisica, Milan Univ., Italy
D. Salvi, Dipt. di Fisica, Milan Univ., Italy
M.G. Sami, Dipt. di Fisica, Milan Univ., Italy
G.R. Sechi, Dipt. di Fisica, Milan Univ., Italy
R. Stefanelli, Dipt. di Fisica, Milan Univ., Italy
pp. 327
T. Horita, Dept. of Comput. & Inf. Sci., Iwate Univ., Morioka, Japan
I. Takanami, Dept. of Comput. & Inf. Sci., Iwate Univ., Morioka, Japan
pp. 335
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