CSDL - Proceedings D

Title Page i (PDF)

pp. i

Title Page iii (PDF)

pp. iii

Title Page iv - copyright (PDF)

pp. iv

Table of Contents (PDF)

pp. v-xv

Message from the General Chairs (PDF)

pp. xvi

Message from the Technical Program Chairs (PDF)

pp. xvii

Organizing Committee (PDF)

pp. xviii-xx

Reviewers (PDF)

pp. xxi

A Design of 14-bits ADC and DAC for CODEC Applications in 0.18 ?m CMOS Process (Abstract)

pp. 3-6

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Compensation-Capacitor Free Pseudo Three-Stage Amplifier with Large Capacitive Loads (Abstract)

Ka Nang Leung

Yanqi Zheng

pp. 7-10

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The Design and Optimization of a 25 kS/s 10 bit Micropower Current S/H Cell for Weak Current Bio-medical Applications (Abstract)

Ka Leong Tsang

Jie Yuan

pp. 11-14

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A Single-Stage SEPIC PFC Converter for Multiple Lighting LED Lamps (Abstract)

pp. 15-19

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Using Genetic Evolutionary Software Application Testing to Verify a DSP SoC (Abstract)

Hu He

pp. 20-25

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Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction (Abstract)

Jia Li

Qiang Xu

pp. 26-31

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Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems (Abstract)

pp. 32-37

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Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications (Abstract)

Hans G. Kerkhoff

Jarkko J. M. Huijts

pp. 38-44

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A Fast Algorithm for the Chirp Rate Estimation (Abstract)

pp. 45-48

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Crack Detection on Asphalt Surface Image Using Enhanced Grid Cell Analysis (Abstract)

Siwaporn Sorncharean

Suebskul Phiphobmongkol

pp. 49-54

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Interpolation Models for Image Super-resolution (Abstract)

pp. 55-60

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Performance Analysis of a Vehicle Crash Control System using Image (Abstract)

Sriram Murali

Ramachandran Shankar

pp. 61-66

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A High Speed CMOS Transmitter and Rail-to-Rail Receiver (Abstract)

Hao Cui

pp. 67-70

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Design of a 12-Channel 120-Gbs Optical Receiver Array in 0.18-?m CMOS Technology (Abstract)

K. Park

pp. 71-74

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99-dB High-Performance Delta-Sigma Modulator for 20-kHz Bandwidth (Abstract)

pp. 75-78

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Analysis and Design of a Continuous-Time Sigma-Delta Modulator with 20 MHz Signal Bandwidth, 53.6 dB Dynamic Range and 51.4 dB SNDR (Abstract)

Tao Wang

Liping Liang

pp. 79-84

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An FPGA Implementation of the Searcher Algorithm (Abstract)

pp. 85-88

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Amith Kumar Nuggehalli Ramachandra

Analysis of CPU Utilisation and Stack Consumption of a Multimedia Embedded System (Abstract)

Avin Kumar Kannur

pp. 89-94

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Research on System Usability of Digital Libraries in China (Abstract)

Yaohua Yu

Zhengjie Liu

pp. 95-98

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A Fast Two-Stage Sample-and-Hold Amplifier for Pipelined ADC Application (Abstract)

Jian Ruan

Chung Len Lee

pp. 99-102

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Low Phase Noise Bond Wire VCO for DVB-H (Abstract)

pp. 103-106

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A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM (Abstract)

pp. 107-110

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A 14-bit 320 MSPS Segmented Current-Steering D/A Converter for High-Speed Applications (Abstract)

pp. 111-114

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A Multiprocessor System for a Small Size Soccer Robot Control System (Abstract)

Ce Li

pp. 115-118

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Low Cost Arbitration Method for Arbitrarily Scalable Multiprocessor Systems (Abstract)

Tero Vallius

Juha R?ning

pp. 119-124

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An Efficient Design of Single Event Transients Tolerance for Logic Circuits (Abstract)

Yantu Mo

Suge Yue

pp. 125-128

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Adaptive Diagnostic Pattern Generation for Scan Chains (Abstract)

Fei Wang

pp. 129-132

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Built-In Self-Test for Embedded Voltage Regulator (Abstract)

Jiang Shi

Ricky Smith

pp. 133-136

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Recent Trends in FPGA Architectures and Applications (Abstract)

Philip H. W. Leong

pp. 137-141

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Embedding Smart Buffers for Window Operations in a Stream-Oriented C-to-VHDL Compiler (Abstract)

pp. 142-147

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Implementation of Hardware Encryption Engine for Wireless Communication on a??Reconfigurable Instruction Cell Architecture (Abstract)

pp. 148-152

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Dynamic Slowdown and Partial Reconfiguration to Optimize Energy in FPGA Based Auto-adaptive SoPC (Abstract)

pp. 153-157

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xDSL Network Upgrade Employing FPGAs (Abstract)

pp. 158-162

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Power Issues on Circuit Design for Cochlear Implants (Abstract)

pp. 163-166

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Architecture of a Low Storage Digital Pixel Sensor Array with an On-Line Block-Based Compression (Abstract)

Milin Zhang

Amine Bermak

pp. 167-170

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Effects of Insulator Thickness on the Sensing Properties of MISiC Schottky-Diode Hydrogen Sensor (Abstract)

pp. 171-174

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High Speed Depth Estimation Using Tilted Focal Planes (Abstract)

Hiroshi Ikeoka

Takayuki Hamamoto

pp. 175-178

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Multi-Phase Charge Pump Generating Positive and Negative High Voltages for TFT-LCD Gate Driving (Abstract)

Chi-Hao Wu

pp. 179-183

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Dynamic Co-operative Intelligent Memory (Abstract)

pp. 184-189

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An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching (Abstract)

pp. 190-195

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Proposal for a Bidirectional Gate Using Pseudo Floating-Gate (Abstract)

O. Mirmotahari

Y. Berg

pp. 196-200

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Read Stability and Write Ability Tradeoff for 6T SRAM Cells in Double-Gate CMOS (Abstract)

Bastien Giraud

Amara Amara

pp. 201-204

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Compact Models for Signal Transient and Crosstalk Noise of Coupled RLC Interconnect Lines with Ramp Inputs (Abstract)

pp. 205-209

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Improving Diagnosis Resolution without Physical Information (Abstract)

pp. 210-215

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Predictive Die-Level Reliability-Yield Modeling for Deep Sub-micron Devices (Abstract)

pp. 216-221

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Hierarchical Calculation of Malicious Faults for Evaluating the Fault-Tolerance (Abstract)

pp. 222-227

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FPGA implementation of a Single Pass Connected Components Algorithm (Abstract)

Christopher T. Johnston

Donald G. Bailey

pp. 228-231

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A Low Voltage Rail-to-Rail OPAMP Design for Biomedical Signal Filtering Applications (Abstract)

Hwang-Cherng Chow

Pu-Nan Weng

pp. 232-235

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Workload-Based Dynamic Voltage Scaling with the QoS for Streaming Video (Abstract)

pp. 236-239

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Speech Recognition of Isolated Malayalam Words Using Wavelet Features and Artificial Neural Network (Abstract)

pp. 240-243

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FPGA Based Real Time Solution for Sensitivity Time Control (Abstract)

D. Meena

L.G.M .Prakasam

pp. 244-248

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A Jittered-Sampling Correction Technique for ADCs (Abstract)

Jamiil Tourabaly

Adam Osseiran

pp. 249-252

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Robust JPEG2000 Image Transmission over IEEE 802.15.4 (Abstract)

pp. 253-257

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New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits (Abstract)

Dong-Shong Liang

Kwang-Jow Gan

pp. 258-261

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Experimental Characterisations of Coupled Transmission Lines (Abstract)

pp. 262-265

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A Low Power Deterministic Test Pattern Generator for BIST Based on Cellular Automata (Abstract)

Bei Cao

Liyi Xiao

Yongsheng Wang

pp. 266-269

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A Test Data Compression Method for System-on-a-Chip (Abstract)

Jianhua Feng

Guoliang Li

pp. 270-273

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A Hybrid of Clonal Selection Algorithm and Frequency Sampling Method for Designing a 2-D FIR Filter (Abstract)

pp. 274-278

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A Generation Flow for Self-Reconfiguration Controllers Customization (Abstract)

Andrea Cuoccio

Paolo R. Grassi

Vincenzo Rana

Marco D. Santambrogio

Donatella Sciuto

pp. 279-284

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Design of High-Speed Floating Point Multiplier (Abstract)

pp. 285-289

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High Performance Elliptic Curve Cryptographic Processor Over GF(2^163) (Abstract)

pp. 290-295

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A Visual Notation for Processor and Resource Scheduling (Abstract)

Christopher T. Johnston

Paul Lyons

Donald G. Bailey

pp. 296-301

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Design for Testability of Functional Cores in High Performance Node Architectures (Abstract)

Venkateswaran Nagarajan

Karthik Chandrasekar

Shrikanth Ganapathy

pp. 302-307

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Test Response Data Volume and Wire Length Reductions for Extended Compatibilities Scan Tree Construction (Abstract)

pp. 308-313

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AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis (Abstract)

pp. 314-321

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Oscillation-Based Test in Data Converters: On-Line Monitoring (Abstract)

Gloria Huertas

Jose L. Huertas

pp. 322-325

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A Case Study on At-Speed Testing for a Gigahertz Microprocessor (Abstract)

Da Wang

Rui Li

Huawei Li

pp. 326-331

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A Charge Pump Circuit --- Cascading High-Voltage Clock Generator (Abstract)

pp. 332-337

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Threshold Voltage Start-up Boost Converter for Sub-mA Applications (Abstract)

pp. 338-341

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Design of a Low-Voltage CMOS Charge Pump (Abstract)

pp. 342-345

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High-Input Impedance Voltage-Mode Universal Biquadratic Filter with One input and Five Outputs Using DDCCs (Abstract)

pp. 346-350

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Temporal-Spatial Correlation Based Mode Decision Algorithm for H.264/AVC Encoder (Abstract)

pp. 351-355

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A Software-to-Hardware Self-Mapping Technique to Enhance Program Throughput for Portable Multimedia Workloads (Abstract)

Allen C. Cheng

pp. 356-361

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Improved Policies for Drowsy Caches in Embedded Processors (Abstract)

pp. 362-367

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Improving Cost-Effectiveness Using a Micro-level Static Architecture for Stream Applications (Abstract)

pp. 368-373

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A Compact CMOS Face Detection Architecture Based on Shunting Inhibitory Convolutional Neural Networks (Abstract)

pp. 374-377

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Temperature Modulation for Tin-Oxide Gas Sensors (Abstract)

A. Far

B. Guo

F. Flitti

A. Bermak

pp. 378-381

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Eigenspectra Palmprint Recognition (Abstract)

pp. 382-385

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VLSI Architecture and FPGA Implementation of a Hybrid Message-Embedded Self-Synchronizing Stream Cipher (Abstract)

pp. 386-389

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DWT/PCA Face Recognition using Automatic Coefficient Selection (Abstract)

Paul Nicholl

Abbes Amira

pp. 390-393

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A Spiking Neural Network for Gas Discrimination Using a Tin Oxide Sensor Array (Abstract)

Bin Guo

pp. 394-397

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A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing (Abstract)

pp. 398-404

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A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow (Abstract)

pp. 405-409

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High-Speed Priority Queue Architecture for Multiple Out Links (Abstract)

pp. 410-414

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Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures (Abstract)

pp. 415-420

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Drift Invariant Gas Recognition Technique for On Chip Tin Oxide Gas Sensor Array (Abstract)

F. Flitti

A. Far

B. Guo

A. Bermak

pp. 421-424

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On Using Fingerprint-Sensors for PIN-Pad Entry (Abstract)

pp. 425-430

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FPGA Implementation of a Predictive Vector Quantization Image Compression Algorithm for Image Sensor Applications (Abstract)

Yan Wang

Amine Bermak

Abdesselam Bouzerdoum

Brian Ng

pp. 431-434

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Integrating Dynamic Load Balancing Strategies into the Car-Network (Abstract)

pp. 435-440

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A Design of the Frequency Synthesizer for UWB Application in 0.13 ?m RF CMOS Process (Abstract)

pp. 441-445

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Analog to Digital Converter Specification for UMTS/FDD Receiver Applications (Abstract)

Zulhakimi Razak

Tughrul Arslan

pp. 446-449

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A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems (Abstract)

Alessio montone

Marco D. Santambrogio

Donatella Sciuto

pp. 450-453

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Bus Binding, Re-ordering, and Encoding for Crosstalk-Producing Switching Activity Minimization during High Level Synthesis (Abstract)

Hariharan Sankaran

Srinivas Katkoori

pp. 454-457

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Scalable Montgomery Multiplier for Finite Fields GF(p) and GF(2^m) (Abstract)

pp. 458-461

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Static Crosstalk Noise Analysis with Transition Map (Abstract)

pp. 462-465

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Implementation of the Embedded System for Visually-Impaired People (Abstract)

pp. 466-469

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Model-Based Gaze Direction Estimation in Office Environment (Abstract)

pp. 470-473

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Fast Evaluation of the Square Root and Other Nonlinear Functions in FPGA (Abstract)

Stefan Lachowicz

Hans-J? Pfleiderer

pp. 474-477

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Configurable Blocks for Multi-precision Multiplication (Abstract)

pp. 478-481

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Shrutisagar Chandrasekaran

High Performance FPGA Implementation of the Mersenne Twister (Abstract)

Abbes Amira

pp. 482-485

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Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips (Abstract)

A. Bouhraoua

M. E. Elrabaa

pp. 486-490

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The Fourier Spectrum Analysis of Optical Feedback Self-Mixing Signal under Weak and Moderate Feedback (Abstract)

pp. 491-495

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Elimination of ? Non-linear Luminance Effects for Digital Video Projection Phase Measuring Profilometers (Abstract)

M. J. Baker

J. Xi

J. F. Chicharo

pp. 496-501

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Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites (Abstract)

pp. 502-505

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Compact Gray-Code Counter/Memory Circuits for Spiking Pixels (Abstract)

pp. 506-511

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Calibration and Debugging of Multi-step Analog to Digital Converters (Abstract)

Amir Zjajo

Jose Pineda de Gyvez

pp. 512-515

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A Prevenient Voltage Stress Test Method for High Density Memory (Abstract)

pp. 516-520

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A Scan-Based Delay Test Method for Reduction of Overtesting (Abstract)

Hui Liu

Huawei Li

pp. 521-526

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An Integrated Validation Environment for Differential Power Analysis (Abstract)

pp. 527-532

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Automated Testing of FlexRay Clusters for System Inconsistencies in Automotive Networks (Abstract)

pp. 533-538

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Early Design Phase Power Performance Trade-Offs Using In-Situ Macro Models (Abstract)

Charles Thangaraj

Tom Chen

pp. 539-544

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Low Voltage Design against Power Analysis Attacks (Abstract)

O. Mirmotahari

Y. Berg

pp. 545-548

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Electrical Power Monitoring System Using Thermochron Sensor and 1-Wire Communication Protocol (Abstract)

pp. 549-554

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Efficient VLSI Layout of Edge Product Networks (Abstract)

Saeedeh Bakhshi

Hamid Sarbazi-Azad

pp. 555-560

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Towards a Petri Net Based Approach to Model and Synthesise Dynamic Reconfiguration for FPGAs (Abstract)

pp. 561-566

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Arbitrary Waveform Generator Based on Direct Digital Frequency Synthesizer (Abstract)

pp. 567-570

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Design of a Data Concentrator Card for the Readout of the Compact Muon Solenoid Electromagnetic Calorimeter (Abstract)

pp. 571-575

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A Novel Approach to High-Level Property Checking Using Wu's Method (Abstract)

pp. 576-580

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Test Set Stripping Limiting the Maximum Number of Specified Bits (Abstract)

Michael A. Kochte

Christian G. Zoellin

Michael E. Imhof

Hans-Joachim Wunderlich

pp. 581-586

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An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling (Abstract)

pp. 587-591

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CreaTe: A New Programme to Attract Engineers as Design Artists (Abstract)

Zsofi Ruttkay

Ton Mouthaan

pp. 592-596

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High-Performance Pseudorandom Number Generator Using Two-Dimensional Cellular Automata (Abstract)

pp. 597-602

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Design Automation of UHF RFID Tag Antenna Design Using a Genetic Algorithm Linked to MWS CST (Abstract)

pp. 603-606

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Author Index (PDF)

pp. 607-610

Roster Page (PDF)

pp. 612