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The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier
Christchurch, New Zealand
January 29-January 31
ISBN: 0-7695-1453-7
S. M. Aziz, University of South Australia
C. N. Basheer, University of South Australia
J. Kamruzzaman, Monash University
This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two's complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating multiplier macros of various operand lengths in different target technologies. A test generation program has been developed for automatic generation of vectors of variable lengths.
Index Terms:
C-Testable, Generic, Modified Booth, Multiplier, VHDL, Synthesis
Citation:
S. M. Aziz, C. N. Basheer, J. Kamruzzaman, "A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier," delta, pp.504, The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02), 2002
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