CSDL Home D DELTA 2002 Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002
Christchurch, New Zealand
Jan. 29, 2002 to Jan. 31, 2002
Vivek Gaur , Avant! Corp.
Vishwani D. Agrawal , Agere Systems
Michael L. Bushnell , Rutgers University
A new transitive closure algorithm is presented for implication graphs that contain partial implications. In the presence of partial implications, a vertex can assume the true state when all vertices that partially imply it become true. Such graphs provide a more complete representation of a logic circuit than is possible with the conventional pair-wise implications. An application of the new transitive closure algorithm to redundancy identification shows significantly improved results. Empirically, we find the computational complexity of transitive closure to be linear for the implication graphs of the ISCAS benchmark circuits.
Implication graph, logic redundancy, partial implications, transitive closure
Vivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell, "A New Transitive Closure Algorithm with Application to Redundancy Identification", DELTA, 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002 2002, pp. 496, doi:10.1109/DELTA.2002.994683